SLVSHC5B November   2023  – July 2024 TPS548D26

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using an External Bias on the VCC and VDRV Pin
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
        1. 6.3.2.1 Fixed VCC_OK UVLO
        2. 6.3.2.2 Fixed VDRV UVLO
        3. 6.3.2.3 Fixed PVIN UVLO
        4. 6.3.2.4 Enable
      3. 6.3.3  Set the Output Voltage
      4. 6.3.4  Differential Remote Sense and Feedback Divider
      5. 6.3.5  Start-Up and Shutdown
      6. 6.3.6  Loop Compensation
      7. 6.3.7  Set Switching Frequency and Operation Mode
      8. 6.3.8  Switching Node (SW)
      9. 6.3.9  Overcurrent Limit and Low-side Current Sense
      10. 6.3.10 Negative Overcurrent Limit
      11. 6.3.11 Zero-Crossing Detection
      12. 6.3.12 Input Overvoltage Protection
      13. 6.3.13 Output Undervoltage and Overvoltage Protection
      14. 6.3.14 Overtemperature Protection
      15. 6.3.15 Power Good
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 6.4.3 Powering the Device From a 12-V Bus
      4. 6.4.4 Powering the Device From a Split-Rail Configuration
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Inductor Selection
        2. 7.2.3.2 Input Capacitor Selection
        3. 7.2.3.3 Output Capacitor Selection
        4. 7.2.3.4 VCC and VRDV Bypass Capacitor
        5. 7.2.3.5 BOOT Capacitor Selection
        6. 7.2.3.6 PG Pullup Resistor Selection
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance on TPS548D26 Evaluation Board
  9. Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Loop Compensation

The TPS548D26 device features D-CAP+ control topology with internal loop compensation for fast transient response. As listed in Table 6-1, two sets of loop compensation are provided for selecting the AC response to load transients. Compensation1 provides a mid-band FB to Inductor Current transconductance of 400S and an integrator zero of 10kHz for applications with less strict compensation requirements and using smaller output capacitors. Compensation2 provides a mid-band FB to Inductor Current transconductance of 1000S and an integrator zero of 2kHz for designs requiring strict transient performance or more output capacitance. Compensation2 of the TPS548D26 is different than Compensation2 of the TPS548C26.

Compensation1 provides a dynamic output impedance of 2.5mOhm × Vout/Vref and a minimum recommended L-C resonance of 5kOhms.

Compensation2 provides a dynamic output impedance of 1mOhm × Vout/Vref and a minimum recommended L-C resonance of 1kOhm.

With either compensation, sufficient output capacitance must be provided such that the output impedance is equal to or less than the dynamic impedance of the selected compensation by no more than ½ of the switching frequency.

To avoid wrong pin strap detection, TI recommends ±1% tolerance resistors with a typical temperature coefficient of ±100 ppm/°C.

Using a Feedfoward Capacitor

Adding a feedforward capacitor to the VOUT to FB divider can reduce the Vout/Vref factor to reduce the dynamic output impedance, but require additional output capacitance. The maximum reduction is 2.5mOhms for Compensation1 and 1mOhm for Compensation2. The exact reduction depends on the impedance divider ratio R1//C1:R2 at the frequency when the output capacitor impedance matches the dynamic impedance.