SLVSHC5B November   2023  – July 2024 TPS548D26

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Internal VCC LDO and Using an External Bias on the VCC and VDRV Pin
      2. 6.3.2  Input Undervoltage Lockout (UVLO)
        1. 6.3.2.1 Fixed VCC_OK UVLO
        2. 6.3.2.2 Fixed VDRV UVLO
        3. 6.3.2.3 Fixed PVIN UVLO
        4. 6.3.2.4 Enable
      3. 6.3.3  Set the Output Voltage
      4. 6.3.4  Differential Remote Sense and Feedback Divider
      5. 6.3.5  Start-Up and Shutdown
      6. 6.3.6  Loop Compensation
      7. 6.3.7  Set Switching Frequency and Operation Mode
      8. 6.3.8  Switching Node (SW)
      9. 6.3.9  Overcurrent Limit and Low-side Current Sense
      10. 6.3.10 Negative Overcurrent Limit
      11. 6.3.11 Zero-Crossing Detection
      12. 6.3.12 Input Overvoltage Protection
      13. 6.3.13 Output Undervoltage and Overvoltage Protection
      14. 6.3.14 Overtemperature Protection
      15. 6.3.15 Power Good
    4. 6.4 Device Functional Modes
      1. 6.4.1 Forced Continuous-Conduction Mode
      2. 6.4.2 Auto-Skip Eco-mode Light Load Operation
      3. 6.4.3 Powering the Device From a 12-V Bus
      4. 6.4.4 Powering the Device From a Split-Rail Configuration
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Application
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
        1. 7.2.3.1 Inductor Selection
        2. 7.2.3.2 Input Capacitor Selection
        3. 7.2.3.3 Output Capacitor Selection
        4. 7.2.3.4 VCC and VRDV Bypass Capacitor
        5. 7.2.3.5 BOOT Capacitor Selection
        6. 7.2.3.6 PG Pullup Resistor Selection
      4. 7.2.4 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
        1. 7.4.2.1 Thermal Performance on TPS548D26 Evaluation Board
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

TJ = –40°C to +125°C. PVIN = 4 V to 16 V, VVCC = 4.5 V to 5.0 V (unless otherwise noted). Typical values are at TJ = 25°C, PVIN = 12 V and VVCC = 4.5 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
PVIN operating input range 4 16 V
AVIN operating input range 4 16 V
IQ(AVIN) AVIN quiescent current Non-switching, PVIN = 12 V, AVIN = 12 V, VEN = 2 V, VFB = VREF + 50 mV, no bias on VCC and VDRV pin 5 6.3 7.5 mA
ISD(PVIN) PVIN shutdown supply current PVIN = 12 V, AVIN = 12 V, VEN = 0 V, no bias on VCC and VDRV pin 20 µA
IVCC VCC and VDRV external bias current External 5-V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 0.6 MHz 32.7 mA
IVCC VCC and VDRV external bias current External 5-V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 0.8 MHz 39.7 mA
IVCC VCC and VDRV external bias current External 5-V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 1.0 MHz 48.7 mA
IVCC VCC and VDRV external bias current External 5-V bias on VCC and VDRV pin, regular switching. TJ = 25°C, PVIN = 12 V, IOUT = 35 A, VEN = 2 V, fSW = 1.2 MHz 57.3 mA
ISD(VCC_VDRV) VCC + VDRV shutdown supply current External 5-V bias on VCC and VDRV pin, PVIN = 12 V, VEN = 0 V  5 6.3 7.5 mA
UVLO
PVINOV PVIN overvoltage rising threshold PVIN rising 18.0 18.6 19.2 V
PVINOV PVIN overvoltage falling threshold PVIN falling. PVIN_OVF status bit, after it is set, cannot be cleared unless PVIN falls below the PVIN overvoltage falling threshold
 12.9 13.4 13.9 V
PVINUVLO(R) PVIN UVLO rising threshold PVIN rising, external 5-V bias on VCC and VDRV pin 2.35 2.55 2.75 V
PVINUVLO(F) PVIN UVLO falling threshold PVIN falling, external 5-V bias on VCC and VDRV pin 2.10 2.30 2.50 V
PVINUVLO(H) PVIN UVLO hysteresis 0.25 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.14 1.19 1.24 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.94 0.98 1.02 V
VEN(H) EN voltage hysteresis 0.21 V
tEN(DIG) EN Deglitch Time 0.2 µs
EN internal pulldown resistor VEN = 2 V, EN pin to AGND 110 125 140 kΩ
INTERNAL VCC LDO
VCC LDO output voltage AVIN = 4 V, IVCC(load) = 5 mA 3.925 3.97 4.0 V
VCC LDO output voltage  AVIN = 5 V to 16 V, IVCC(load) = 5 mA 4.28 4.44 4.55 V
VCC LDO dropout voltage  AVIN – VVCC, AVIN = 4 V, IVCC(load) = 50 mA 160.8 280 mV
VCC_OK rising threshold TJ = –40°C to 85°C. VCC rising, enabling initial power-on including re-loading default values from NVM 3.0 3.15 3.3 V
VCC_OK falling threshold TJ = –40°C to 85°C. VCC falling, disabling controller circuit including the memory and the digital engine 2.95 3.10 3.25 V
VCC LDO short-circuit current limit  150 mA
REFERENCE VOLTAGE
VFB FB voltage TJ = 0°C to 85°C  594 600 603 mV
VFB FB voltage TJ = –40°C to 125°C 591 600 606 mV
IFB(LKG) FB input leakage current VFB = 600 mV 10 nA
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 0 Ω 540 600 660 kHz
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 1.5 kΩ 720 800 880 kHz
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 14 kΩ 900 1000 1100 kHz
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = 16.2 kΩ 1080 1200 1320 kHz
fSW(FCCM) Switching frequency, FCCM operation TJ = –40°C to 125°C, PVIN = 12 V, VOUT = 1.1 V, no load, RMODE = float 720 800 880 kHz
STARTUP AND SHUTDOWN
tON(DLY) Power on sequence delay VVCC = 4.5 V 0.5 0.55 ms
tON(Rise) Soft-start time VVCC = 4.5 V, RSS = AGND 0.75 0.825 ms
tON(Rise) Soft-start time VVCC = 4.5 V, RSS = 5.76 kΩ 1.5 1.65 ms
tON(Rise) Soft-start time VVCC = 4.5 V, RSS = 14 kΩ 3 3.3 ms
tON(Rise) Soft-start time VVCC = 4.5 V, RSS = 28.7 kΩ 6 6.6 ms
tON(Rise) Soft-start time VVCC = 4.5 V, RSS = open 3 3.3 ms
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VBOOT-SW = 4.5 V 4 mΩ
RDSON(HS) High-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VBOOT-SW = 5.0 V 3.91 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VVDRV = 4.5 V 1 mΩ
RDSON(LS) Low-side MOSFET on-resistance TJ = 25°C, PVIN = 12 V, VVDRV = 5 V 0.98 mΩ
tON(min) Minimum ON pulse width VVCC = 4.5 V 60 ns
tOFF(min) Minimum OFF pulse width VVCC = 4.5 V, IOUT = 1.5 A, VVOSNS = VOUT_Setting – 20 mV, SW falling edge to rising edge 210 250 ns
BOOT CIRCUIT
IBOOT(LKG) BOOT leakage current VEN = 2 V, VBOOT-SW = 5 V 150 µA
VBOOT-SW(UV_F) BOOT-SW UVLO falling threshold 2.60 2.76 V
OVERCURRENT LIMIT
ILS(OCL) Low-side valley overcurrent limit Valley current limit on LS FET, RILIM = 7.5 kΩ 11.5 13.4 16 A
ILS(OCL) Low-side valley overcurrent limit Valley current limit on LS FET, RILIM = 12.1 kΩ 18.8 21 23.3 A
ILS(OCL) Low-side valley overcurrent limit Valley current limit on LS FET, RILIM = 16.2 kΩ 25.5 28.5 31.5 A
ILS(OCL) Low-side valley overcurrent limit Valley current limit on LS FET, RILIM = 21.5 kΩ 32.8 36.5 40.3 A
ILS(OCL) Low-side valley overcurrent limit Valley current limit on LS FET, RILIM = 24.9 kΩ 39 43 47.5 A
ILS(NOC) Low-side negative overcurrent limit Sinking current limit on LS FET –20 –17.6 –15.4 A
IZC Zero-cross detection current threshold ZC comparator threshold, enter DCM. PVIN = 12 V, VVCC = 4.5 V 1200 mA
Response delay before entering Hiccup 16 20 µs
Hiccup sleep time before a restart 49 56 59 ms
OUTPUT OVP AND UVP
VOVF VOUT Overvoltage-protection (OVP) threshold (VFB –  VGOSNS) and rising 118.33% 125% 130%
OVF response delay From OVF detection to the start of the NOC operation 100 ns
VUVF VOUT Undervoltage-protection (UVP) threshold (VFB –  VGOSNS) and falling 60% 66.67% 73.33%
UVF response delay From UVF detection to tri-state of the power FETs 16 20 µs
POWER GOOD
VOL(PG) PG pin output low-level voltage IPG = 10 mA, PVIN = 12 V, VVCC = 4.5 V 300 mV
ILKG(PG) PG pin Leakage current when open drain output is high Rpullup = 10 kΩ, VPG = 5 V 5 µA
Minimum VCC for valid PG pin output PVIN = 0 V, VEN = 0 V, Rpullup = 10 kΩ, VPG ≤ 0.3 V  1.2 V
OUTPUT DISCHARGE
Output discharge on VOSNS pin PVIN = 12 V, VVCC = 4.5 V, VVOSNS = 0.5 V, EN=0V 455 Ω
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown (Analog OTP) threshold (1) Junction temperature rising 153 166 °C
TJ(HYS) Thermal shutdown (Analog OTP) hysteresis (1) 30 °C
(1) These parameters are provided for reference only, and do not constitute part of TI's published device specifications for purpose of TI's product warranty.