SLVSHM2B March   2025  – October 2026 TPS2HC120-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SNS Timing Characteristics
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Current and Voltage Conventions
      2. 7.3.2 Low Power Mode
        1. 7.3.2.1 Entry Into LPM
        2. 7.3.2.2 During LPM
        3. 7.3.2.3 Exiting LPM
      3. 7.3.3 Accurate Current Sense
      4. 7.3.4 Adjustable Current Limit
      5. 7.3.5 Inductive-Load Switching-Off Clamp
      6. 7.3.6 Fault Detection and Reporting
        1. 7.3.6.1 Diagnostic Enable Function
        2. 7.3.6.2 Multiplexing of Current Sense
        3. 7.3.6.3 FLT Reporting
        4. 7.3.6.4 Fault Table
      7. 7.3.7 Full Diagnostics
        1. 7.3.7.1 Short-to-GND and Overload Detection
        2. 7.3.7.2 Open-Load Detection
          1. 7.3.7.2.1 Channel On
          2. 7.3.7.2.2 Channel Off
        3. 7.3.7.3 Short-to-Battery Detection
        4. 7.3.7.4 Reverse-Polarity and Battery Protection
        5. 7.3.7.5 Thermal Fault Detection
          1. 7.3.7.5.1 Thermal Protection Behavior
      8. 7.3.8 Full Protections
        1. 7.3.8.1 UVLO Protection
        2. 7.3.8.2 Loss of GND Protection
        3. 7.3.8.3 Loss of Power Supply Protection
        4. 7.3.8.4 Reverse Battery Protection
        5. 7.3.8.5 Protection for MCU I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Working Modes
        1. 7.4.1.1 SLEEP
        2. 7.4.1.2 DIAGNOSTIC
        3. 7.4.1.3 ACTIVE
        4. 7.4.1.4 STANDBY DELAY
        5. 7.4.1.5 LOW POWER MODE
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 EMC Transient Disturbances Test
    3. 8.3 Typical Application
      1. 8.3.1 Design Requirements
      2. 8.3.2 Detailed Design Procedure
      3. 8.3.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Examples
        1. 8.5.2.1 Without a GND Network
        2. 8.5.2.2 With a GND Network
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.2.2 During LPM

The quiescent current of the device during LPM, IQ,LPM, is a function of how many channels are active and is proportional to the load current meaning that the lower the load current during this time, the lower the quiescent current is. Additionally, since the digital core is disabled, the diagnostics like current sensing or open load detection are not available during this mode. If diagnostics are desired, the DIAG_EN pin can be enabled to exit LPM and return the part back to normal operation. Once DIAG_EN is disabled the device goes back into LPM after tSTBY. Similarly, the current limit mechanism is not active in the same manner as by definition the minimum current limit is higher than the entry point of LPM. However, the short-circuit protection is still in place to protect the device.

Below is the summary of the behavior of the device during LPM:

  • Iq reduces to IQ,LPM per channel
  • RDS,ON per channel increases to RDSON,LPM
  • No clamped current limit for overload conditions as the device exits the LPM first
  • Short-circuit protection is in place to shut off the device if load current increases to IPKLPM,SC during LPM
  • No thermal shutdown protection