SLVSHP9 July   2026 TPS544A28

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP4 Control
      2. 7.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 7.3.2.1 Powering the Device From a Single Bus
        2. 7.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 7.3.3  Multifunction Select (MS1) Pin
      4. 7.3.4  Multifunction Select (MS2) Pin
      5. 7.3.5  PMBus® Address (ADR) Pin
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Setting VBOOT and VOUT_SCALE_LOOP
        2. 7.3.6.2 Setting Output Voltage (Internal Feedback)
        3. 7.3.6.3 Setting Output Voltage (External Feedback)
      7. 7.3.7  Switching Frequency
      8. 7.3.8  Dynamic Voltage Slew Rate
      9. 7.3.9  Enable
      10. 7.3.10 Soft Start and Soft Stop
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Remote Sense
      14. 7.3.14 Low-side MOSFET Zero-Crossing
      15. 7.3.15 Current Sense and Positive Overcurrent Protection
      16. 7.3.16 Low-side MOSFET Negative Current Limit
      17. 7.3.17 Output Voltage Discharge
      18. 7.3.18 UVLO Protection
      19. 7.3.19 Telemetry
      20. 7.3.20 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  9. 8 Programming Registers
    1. 8.1 Register Map
      1. 8.1.1  OPERATION (Address = 01h)
      2. 8.1.2  ON_OFF_CONFIG (Address = 02h)
      3. 8.1.3  CLEAR_FAULTS (Address = 03h)
      4. 8.1.4  WRITE_PROTECT (Address = 10h)
      5. 8.1.5  STORE_USER_ALL (Address = 15h)
      6. 8.1.6  RESTORE_USER_ALL (Address = 16h)
      7. 8.1.7  CAPABILITY (Address = 19h)
      8. 8.1.8  VOUT_MODE (Address = 20h)
      9. 8.1.9  VOUT_COMMAND (Address = 21h)
      10.      57
      11. 8.1.10 VOUT_MARGIN_HIGH (Address = 25h)
      12. 8.1.11 VOUT_MARGIN_LOW (Address = 26h)
      13. 8.1.12 VOUT_TRANSITION_RATE (Address = 27h)
      14. 8.1.13 61
      15. 8.1.14 VOUT_SCALE_LOOP (Address = 29h)
      16. 8.1.15 FREQUENCY_SWITCH (Address = 33h)
      17. 8.1.16 64
      18. 8.1.17 VOUT_OV_FAULT_RESPONSE (Address = 41h)
      19. 8.1.18 VOUT_UV_FAULT_RESPONSE (Address = 45h)
      20. 8.1.19 IOUT_OC_FAULT_LIMIT (Address = 46h)
      21.      68
      22. 8.1.20 TON_DELAY (Address = 60h)
      23. 8.1.21 TON_RISE (Address = 61h)
      24.      71
      25. 8.1.22 TOFF_DELAY (Address = 64h)
      26. 8.1.23 TOFF_FALL (Address = 65h)
      27. 8.1.24 STATUS_BYTE (Address = 78h)
      28. 8.1.25 STATUS_WORD (Address = 79h)
      29. 8.1.26 STATUS_CML (Address = 7Eh)
      30. 8.1.27 STATUS_MFR_SPECIFIC (Address = 80h)
      31. 8.1.28 READ_VOUT (Address = 8Bh)
      32. 8.1.29 READ_IOUT (Address = 8Ch)
      33. 8.1.30 READ_TEMP1 (Address = 8Dh)
      34. 8.1.31 PMBUS_REVISION (Address = 98h)
      35. 8.1.32 MFR_ID (Address = 99h)
      36. 8.1.33 MFR_MODEL (Address = 9Ah)
      37. 8.1.34 MFR_REVISION (Address = 9Bh)
      38. 8.1.35 IC_DEVICE_ID (Address = ADh)
      39. 8.1.36 IC_DEVICE_REV (Address = AEh)
      40. 8.1.37 SYS_CFG_USER1 (Address = D1h)
      41. 8.1.38 PASSKEY (Address = D2h)
      42. 8.1.39 COMP (Address = D4h)
      43.      90
      44. 8.1.40 VBOOT (Address = D5h)
      45.      92
      46. 8.1.41 NVM_CHECKSUM (Address = D9h)
      47. 8.1.42 FUSION_ID0 (Address = FCh)
      48. 8.1.43 FUSION_ID1 (Address = FDh)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting Point
        2. 9.2.2.2 Choose the Switching Frequency
        3. 9.2.2.3 Choose the Inductor
        4. 9.2.2.4 Choose the Output Capacitor
        5. 9.2.2.5 Choose the Input Capacitors (CIN)
        6. 9.2.2.6 VCC Bypass Capacitor
        7. 9.2.2.7 BOOT Capacitor
        8. 9.2.2.8 PG Pullup Resistor
        9. 9.2.2.9 Choose the PMBus® Address and Fault Recovery Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Performance On TI EVM
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.5 Electrical Characteristics

TJ = –40°C to +150°C, VVCC = 3.3V (external), VVIN = 4V to 16V. Typical values are at TJ = 25°C and VVIN = 12V (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ(VIN) VIN quiescent current Non-switching, VEN = 2V, VFB = VFB_REG + 50mV, no external bias on VCC pin 2800 µA
IQ(VIN) VIN quiescent current with external VCC bias TJ = 25°C, VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3V external bias on VCC pin 250 400 µA
IQ(VCC) VCC quiescent current TJ = 25°C, VIN = 12V, VEN = 2V, VFB = VFB_REG + 10mV (non-switching), 3.3V external bias on VCC pin 2500 4500 µA
IVCC VCC external bias current(1) TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, VOUT = 1.0V, fSW = 600kHz, 3.3V external bias on VCC pin 10 mA
IVCC VCC external bias current(1) TJ = 25°C, VIN = 12V, VEN = 2V, regular switching, VOUT = 1.0V, fSW = 1200kHz, 3.3V external bias on VCC pin 16 mA
INTERNAL LDO (VCC)
VVCC Internal LDO output voltage 2.85 3.0 3.1 V
IVCC Internal LDO short-circuit current limit VVIN = 12V 50 180 mA
UVLO
VINUVLO(R) VIN UVLO rising threshold VIN rising, 3.3V external bias on VCC pin 2.35 2.4 2.5 V
VINUVLO(F) VIN UVLO falling threshold VIN falling, 3.3V external bias on VCC pin 2.3 2.35 2.4 V
VINUVLO(H) VIN UVLO hysteresis 0.15 V
ENABLE
VEN(R) EN voltage rising threshold EN rising, enable switching 1.15 1.2 1.25 V
VEN(F) EN voltage falling threshold EN falling, disable switching 0.95 1.0 1.05 V
VEN(H) EN voltage hysteresis 200 mV
IEN(Hys) EN pin hysteresis current EN > VEN(R) 5 µA
EN internal pull-down resistance EN pin to AGND 0.74 1 1.27 MΩ
PINSTRAP
RMSx_TRIP MSx resistor step range accuracy –2%  + 2%
SERIAL INTERFACE
VIH(SDx) High-level input voltage on SDA, SCL 1.35 V
VIL(SDx) Low-level input voltage on SCL, SDA 0.8
Vth_rise(SDx) Rising Threshold SCL, SDA 1.03 1.1 1.17 V
Vth_fall(SDx) Falling Threshold on SCL, SDA 0.84 0.9 0.96 V
Vth_hys(SDx) Hysteresis on SCL, SDA 0.188 0.2 0.212 V
IlH(SDx) Input high level current into SCL, SDA –10 10 µA
IIL(SDx) Input low level current into SCL, SDA –10 10 µA
VOL(SDx) Output low level voltage on SDA VCC ≥ 4.5V, Ipin = 20mA 0.4 V
IOH(SDx) Output high level open drain leakage current into SDA Vpin = 5.5V 10 µA
IOL(SDx) Output low level open drain sinking current on PMB_DATA Vpin = 0.4V 20 mA
CPIN_SDx SCL and SDA pin input capacitance (1) Vpin = 0.1V to 1.35V 5 pF
fSDxmin Minimum PMBus operating Frequency 10 kHz
fSDxmax Maximum PMBus operating Frequency 1000 kHz
fSDx_CLK PMBus operating frequency range 10 1000 kHz
tBUF Bus free time between a STOP and START condition 0.5 µs
tHD_STA Hold time for a (repeated) START condition 0.26 µs
tSU_STA Setup time for a repeated START condition 0.26 µs
tSU_STO Setup time for a STOP condition 0.26 µs
tHD_SDA SDA hold time 0 µs
tSU_SDA SDA setup time 50 ns
tTIMEOUT Detect clock low timeout 25 30 35 ms
tLOW Low period of SCL 0.5 µs
tHIGH High period of SCL 0.26 µs
tR_SDx SCL and SDA rise time (1) 1000kHz class; VIL(MAX) - 150mV to VIH(MIN) + 150mV 120 ns
tF_SDx SCL and SDA fall time(1) 1000kHz class; VIH(MIN) + 150mV to VIL(MAX) - 150mV 120 ns
NWR_NVM Number of NVM writeable cycles(1) –40°C ≤ TJ ≤ 125°C 1000 cycle
START-UP
RPIN-STRAP Pin-strap resistor step range accuracy 0.82kΩ ≤ RPIN-STRAP ≤ 82kΩ –4% +4%
tSS Soft-start time(1) From start of switching to VFB = 0.5V, tSS = 0.5ms setting 0.4 0.5 0.6 ms
tSS Soft-start time(1) From start of switching to VFB = 0.5V, tSS = 1ms setting 0.8 1 1.2 ms
tSS Soft-start time(1) From start of switching to VFB = 0.5V, tSS = 2ms setting 1.6 2 2.4 ms
tSS Soft-start time From start of switching to VFB = 0.5V, tSS = 4ms setting 3.2 4 4.8 ms
tEN_DLY EN HIGH to start of switching delay TON_Delay = 0 50 µs
REFERENCE VOLTAGE (FB)
VVOS_REG Output voltage regulation accuracy Internal Feedback Configuration, TJ = 0°C to +85°C, VOSL = 1 or 0.5 –0.5% +0.5%
VVOS_REG Output voltage regulation accuracy Internal Feedback Configuration, VOSL = 1 or 0.5 –0.75% + 0.75%
VVOS_REG Output voltage regulation accuracy Internal Feedback Configuration, TJ = 0°C to +85°C, VOSL = 0.25 or 0.125 –0.75% + 0.75%
VVOS_REG Output voltage regulation accuracy Internal Feedback Configuration, VOSL = 0.25 or 0.125 –1% +1%
VFB_REG Feedback voltage regulation accuracy External Feedback Configuration, TJ = 0°C to +85°C –0.5% +0.5%
VFB_REG Feedback voltage regulation accuracy External Feedback Configuration –0.75% + 0.75%
IFB(LKG) FB input leakage current VFB = VFB_REG 160 nA
DIFFERENTIAL REMOTE SENSE AMPLIFIER
IGOSNS Leakage current out of GOS pin VGOS - VAGND = 100mV 80 µA
VICM GOS common mode voltage for regulation(1) VGOS versus VAGND –0.1 0.1 V
TELEMETRY
MIOUT(rng) Output current measurement range 0 14 A
MIOUT(acc) Output current measurement accuracy 3A < IOUT ≤ 6A –10% 10%
6A < IOUT ≤ 12A –7.5% 7.5%
MIOUT(off) Output current measurement offset IOUT ≤ 3A –0.6 0.6 A
MVOUT(rng) Output voltage measurement range 0 6 V
MVOUT(acc) Output voltage measurement accuracy 400mV ≤ VOUT ≤ 5.5V –2% 2%
MVOUT(lsb) Output voltage measurement bit resolution 1 mV
MTSNS(rng) Internal temperature sense range(1) –40 150 °C
MTSNS(lsb) Internal temperature sense bit resolution, (8Dh) READ_TEMP1 1 °C
MTSNS(acc) Internal temperature sense accuracy –40°C ≤ TJ ≤ 150°C –1.5 +2.5 +6.5 °C
SWITCHING FREQUENCY
fSW(FCCM) Switching frequency, FCCM operation VVIN = 12V, VOUT = 3.3V, FSW = 500kHz, No load 425 500 575 kHz
fSW(FCCM) Switching frequency, FCCM operation VVIN = 12V, VOUT = 3.3V, FSW = 600kHz, No load 510 600 690 kHz
fSW(FCCM) Switching frequency, FCCM operation(1) VVIN = 12V, VOUT = 3.3V, FSW = 800kHz, No load 680 800 920 kHz
fSW(FCCM) Switching frequency, FCCM operation VVIN = 12V, VOUT = 3.3V, FSW = 1.0MHz, No load 850 1000 1150 kHz
fSW(FCCM) Switching frequency, FCCM operation(1) VVIN = 12V, VOUT = 3.3V, FSW = 1.2MHz, No load 1020 1200 1380 kHz
fSW(FCCM) Switching frequency, FCCM operation VVIN = 12V, VOUT = 3.3V, FSW = 1.4MHz, No load 1190 1400 1610 kHz
POWER STAGE
RDSON(HS) High-side MOSFET on-resistance VBOOT-SW = 3.3V 8.5 mΩ
RDSON(LS) Low-side MOSFET on-resistance VVCC = 3.3V 3.0 mΩ
tON(min) Minimum ON pulse width(1) 25 ns
tOFF(min) Minimum OFF pulse width(1) 150 ns
Output discharge MOSFET on-resistance VIN = 12V, VSW = 1V, power conversion disabled 100 Ω
IBOOT(LKG) Leakage current into BOOT pin VBOOT-SW = 3V, Enabled, Not switching. 30 µA
POWER GOOD
VPGTH(RISE_OV) Power-Good threshold FB rising, PG high to low 105% 110% 116.4%
VPGTH(RISE_UV) Power-Good threshold FB rising, PG low to high 84.9% 90% 96.4%
VPGTH(FALL_UV) Power-Good threshold FB falling, PG high to low 79.2% 85% 91.7%
tPG_DLY PG delay going from low to high during startup 1.1 1.5 ms
PG delay going from high to low 4 6.2 µs
IPG(LKG) PG pin leakage current when open drain output is high VPG = 4.5V 5 µA
PG pin output low-level voltage IPG = 7mA 600 mV
PG pin output low-level when VIN and VCC are low   VVIN = 0V, VVCC = 0V, VEN = 0V, PG pulled up to 3.3V through a 100kΩ resistor 940 mV
PG pin output low-level when VIN and VCC are low   VVIN = 0V, VVCC = 0V, VEN = 0V, PG pulled up to 3.3V through a 10kΩ resistor 1100 mV
OVERCURRENT PROTECTION
Low-side valley current limit Valley current on LS FET, RMS1  = GND 11.5 13 14.5 A
Valley current on LS FET, RMS1 = 4.7kΩ(1) 9 10 11 A
Valley current on LS FET, RMS1 = 22kΩ(1) 6 7 8 A
Valley current on LS FET, RMS1 = 56kΩ(1) 3 4 5 A
ILS(NOC) Low-side negative current limit Sinking current limit on LS FET –6 –4 A
IZC Zero-cross detection current threshold to enter DCM, open loop VIN = 12V –750 mA
IZC(HYS) Zero-cross detection current threshold hysteresis after entering DCM, open loop VIN = 12V 1000 mA
OUTPUT OVP AND UVP
VOVP_FIX Fixed Overvoltage-protection (OVP) threshold voltage VFB rising, VOUT_SCALE_LOOP = 1 1.1 V
VOVP_FIX Fixed Overvoltage-protection (OVP) threshold voltage VFB rising, VOUT_SCALE_LOOP = 0.5 2.2 V
VOVP_FIX Fixed Overvoltage-protection (OVP) threshold voltage VFB rising, VOUT_SCALE_LOOP = 0.25 4.4 V
VOVP_FIX Fixed Overvoltage-protection (OVP) threshold voltage VFB rising, VOUT_SCALE_LOOP = 0.125 6.6 V
VOVP Overvoltage-protection (OVP) threshold voltage VFB rising 107% 116% 125%
tOVPDLY OVP delay With 100mV overdrive 400 ns
VUVP Undervoltage-protection (UVP) threshold voltage VFB falling 73.9% 80% 87%
tUVPDLY UVP filter delay 70 µs
Hiccup wait time Hiccup mode enabled 56 ms
THERMAL SHUTDOWN
TJ(SD) Thermal shutdown threshold (1) Temperature rising 165 °C
TJ(HYS) Thermal shutdown hysteresis (1) 15 °C
(1) Specified by design; not tested in production.