SLVSHP9 July   2026 TPS544A28

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Related Products
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  D-CAP4 Control
      2. 7.3.2  Internal VCC LDO and Using External Bias On the VCC Pin
        1. 7.3.2.1 Powering the Device From a Single Bus
        2. 7.3.2.2 Powering the Device From a Split-Rail Configuration
      3. 7.3.3  Multifunction Select (MS1) Pin
      4. 7.3.4  Multifunction Select (MS2) Pin
      5. 7.3.5  PMBus® Address (ADR) Pin
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Setting VBOOT and VOUT_SCALE_LOOP
        2. 7.3.6.2 Setting Output Voltage (Internal Feedback)
        3. 7.3.6.3 Setting Output Voltage (External Feedback)
      7. 7.3.7  Switching Frequency
      8. 7.3.8  Dynamic Voltage Slew Rate
      9. 7.3.9  Enable
      10. 7.3.10 Soft Start and Soft Stop
      11. 7.3.11 Power Good
      12. 7.3.12 Overvoltage and Undervoltage Protection
      13. 7.3.13 Remote Sense
      14. 7.3.14 Low-side MOSFET Zero-Crossing
      15. 7.3.15 Current Sense and Positive Overcurrent Protection
      16. 7.3.16 Low-side MOSFET Negative Current Limit
      17. 7.3.17 Output Voltage Discharge
      18. 7.3.18 UVLO Protection
      19. 7.3.19 Telemetry
      20. 7.3.20 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Auto-Skip (PFM) Eco-mode Light Load Operation
      2. 7.4.2 Forced Continuous-Conduction Mode
  9. Programming Registers
    1. 8.1 Register Map
      1. 8.1.1  OPERATION (Address = 01h)
      2. 8.1.2  ON_OFF_CONFIG (Address = 02h)
      3. 8.1.3  CLEAR_FAULTS (Address = 03h)
      4. 8.1.4  WRITE_PROTECT (Address = 10h)
      5. 8.1.5  STORE_USER_ALL (Address = 15h)
      6. 8.1.6  RESTORE_USER_ALL (Address = 16h)
      7. 8.1.7  CAPABILITY (Address = 19h)
      8. 8.1.8  VOUT_MODE (Address = 20h)
      9. 8.1.9  VOUT_COMMAND (Address = 21h)
      10.      57
      11. 8.1.10 VOUT_MARGIN_HIGH (Address = 25h)
      12. 8.1.11 VOUT_MARGIN_LOW (Address = 26h)
      13. 8.1.12 VOUT_TRANSITION_RATE (Address = 27h)
      14. 8.1.13 61
      15. 8.1.14 VOUT_SCALE_LOOP (Address = 29h)
      16. 8.1.15 FREQUENCY_SWITCH (Address = 33h)
      17. 8.1.16 64
      18. 8.1.17 VOUT_OV_FAULT_RESPONSE (Address = 41h)
      19. 8.1.18 VOUT_UV_FAULT_RESPONSE (Address = 45h)
      20. 8.1.19 IOUT_OC_FAULT_LIMIT (Address = 46h)
      21.      68
      22. 8.1.20 TON_DELAY (Address = 60h)
      23. 8.1.21 TON_RISE (Address = 61h)
      24.      71
      25. 8.1.22 TOFF_DELAY (Address = 64h)
      26. 8.1.23 TOFF_FALL (Address = 65h)
      27. 8.1.24 STATUS_BYTE (Address = 78h)
      28. 8.1.25 STATUS_WORD (Address = 79h)
      29. 8.1.26 STATUS_CML (Address = 7Eh)
      30. 8.1.27 STATUS_MFR_SPECIFIC (Address = 80h)
      31. 8.1.28 READ_VOUT (Address = 8Bh)
      32. 8.1.29 READ_IOUT (Address = 8Ch)
      33. 8.1.30 READ_TEMP1 (Address = 8Dh)
      34. 8.1.31 PMBUS_REVISION (Address = 98h)
      35. 8.1.32 MFR_ID (Address = 99h)
      36. 8.1.33 MFR_MODEL (Address = 9Ah)
      37. 8.1.34 MFR_REVISION (Address = 9Bh)
      38. 8.1.35 IC_DEVICE_ID (Address = ADh)
      39. 8.1.36 IC_DEVICE_REV (Address = AEh)
      40. 8.1.37 SYS_CFG_USER1 (Address = D1h)
      41. 8.1.38 PASSKEY (Address = D2h)
      42. 8.1.39 COMP (Address = D4h)
      43.      90
      44. 8.1.40 VBOOT (Address = D5h)
      45.      92
      46. 8.1.41 NVM_CHECKSUM (Address = D9h)
      47. 8.1.42 FUSION_ID0 (Address = FCh)
      48. 8.1.43 FUSION_ID1 (Address = FDh)
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Voltage Setting Point
        2. 9.2.2.2 Choose the Switching Frequency
        3. 9.2.2.3 Choose the Inductor
        4. 9.2.2.4 Choose the Output Capacitor
        5. 9.2.2.5 Choose the Input Capacitors (CIN)
        6. 9.2.2.6 VCC Bypass Capacitor
        7. 9.2.2.7 BOOT Capacitor
        8. 9.2.2.8 PG Pullup Resistor
        9. 9.2.2.9 Choose the PMBus® Address and Fault Recovery Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
      3. 9.4.3 Thermal Performance On TI EVM
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Choose the Output Capacitor

There are three considerations for selecting the value of the output capacitor:
  1. Stability
  2. Steady state output voltage ripple
  3. Regulator transient response to a change load current
First, calculate the minimum output capacitance based on these three requirements. Equation 14 calculates the minimum capacitance to keep the LC double pole below the fP(MAX) in Table 7-2 to meet stability requirements. To calculate the fP(MAX), locate the correct Kf_LC in Table 7-2. By default, this part comes pre-programmed with RAMP3 and SEL_SUMCOMP = 0 as it's compensation settings. In this example, Kf_LC = 9.6 and VREF_DAC = VOUT_COMMAND × VOSL = 3.3V × 0.125V/V = 0.4125V. After you determine the correct Kf_LC and VREF_DAC, plug both values into Equation 2. For this example application, fP(MAX) = 14.947kHz. Plug the calculated fP(MAX) into Equation 14 to determine your minimum required Cout for stability. Equation 15 calculates the minimum capacitance to meet the steady state output voltage ripple requirement of 16mV. These calculations are for CCM operation and does not include the portion of the output voltage ripple caused by the ESR or ESL of the output capacitors.
Equation 14. C O U T _ S T A B L I T Y > 1 2 π × f P ( M A X ) 2 × 1 L O U T = 1 2 π × 14.947 k H z 2 × 1 0.55 μ H = 207 μ F
Equation 15. C O U T _ R I P P L E > I R I P P L E 8 × V R I P P L E × f S W = 5.95 A 8 × 16 m V × 800 k H z = 58.1 μ F

Equation 17and Equation 18 calculate the minimum capacitance to meet the transient response requirement of 99mV with a 10A step. These equations calculate the necessary output capacitance to hold the output voltage steady while the inductor current ramps up or ramps down after a load step.

Equation 16. C O U T _ U N D E R S H O O T > L × I S T E P 2 × V O U T V I N m i n × f S W + t O F F _ M I N m a x 2 × V T R A N S × V O U T × V I N m i n - V O U T V I N m i n × f S W - t O F F _ M I N m a x
Equation 17. C O U T _ U N D E R S H O O T > 0.55 μ H × 10 A 2 × 3.3 V 8 V × 800 k H z + 150 n s 2 × 99 m V × 3.3 V × 8 V - 3.3 V 8 V × 800 k H z - 150 n s = 95.9 μ F
Equation 18. C O U T _ O V E R S H O O T > L × I S T E P 2 2 × V T R A N S × V O U T = 0.55 μ H × 10 A 2 2 × 99 m V × 3.3 V = 84.2 μ F

The output capacitance needed to meet the overshoot requirement is the highest value, so this sets the required minimum output capacitance for this example. Stability requirements can also limit the maximum output capacitance. Equation 19 calculates the recommended maximum output capacitance. This calculation keeps the LC double pole above 1/100th the fSW.

Equation 19. C O U T _ S T A B I L I T Y < 50 π × f S W 2 × 1 L = 50 π × 800 k H z 2 × 1 0.55 μ H = 720 μ F

Using more output capacitance is possible, but the stability must be checked through a bode plot or transient response measurement. The selected output capacitance is 6 × 47μF, 10V ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to DC and AC bias effects. The selected capacitors derate to 75% the nominal value giving an effective total capacitance of 211μF. This effective capacitance meets the minimum and maximum requirements.

This application uses all ceramic capacitors so the effects of ESR on the ripple and transient are ignored. If using non ceramic capacitors, as a starting point, the ESR must be below the values calculated in Equation 20 to meet the ripple requirement and Equation 21 to meet the transient requirement. For more accurate calculations or if using mixed output capacitors, the impedance of the output capacitors must be used to determine if the ripple and transient requirements can be met.

Equation 20. R E S R _ R I P P L E < V R I P P L E I R I P P L E = 26 m V 5.95 A = 4.4 m Ω
Equation 21. R E S R _ T R A N S < V T R A N S I S T E P = 99 m V 10 A = 9.9 m Ω