SLVSIH3
July 2025
TPS546B25W
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
D-CAP4 Control
6.3.1.1
Loop Compensation
6.3.2
Internal VCC LDO and Using an External Bias on the VDRV Pin
6.3.3
Input Undervoltage Lockout (UVLO)
6.3.3.1
Fixed VCC_OK UVLO
6.3.3.2
Fixed VDRV UVLO
6.3.3.3
Programmable PVIN UVLO
6.3.3.4
Control (CNTL) Enable
6.3.4
Differential Remote Sense and Internal, External Feedback Divider
6.3.5
Set the Output Voltage and VORST#
6.3.6
Start-Up and Shutdown
6.3.7
Dynamic Voltage Slew Rate
6.3.8
Set Switching Frequency
6.3.9
Switching Node (SW)
6.3.10
Overcurrent Limit and Low-side Current Sense
6.3.11
Negative Overcurrent Limit
6.3.12
Zero-Crossing Detection
6.3.13
Input Overvoltage Protection
6.3.14
Output Overvoltage and Undervoltage Protection
6.3.15
Overtemperature Protection
6.3.16
Telemetry
6.4
Device Functional Modes
6.4.1
Forced Continuous-Conduction Mode
6.4.2
DCM Light Load Operation
6.4.3
Powering the Device From a 12V Bus
6.4.4
Powering the Device From a Split-rail Configuration
6.4.5
Pin-Strapping
6.4.5.1
Programming MSEL1
6.4.5.2
Programming PMB_ADDR
6.4.5.3
Programming MSEL2
6.4.5.4
Programming VSEL\FB
6.5
Programming
6.5.1
Supported PMBus® Commands
7
Register Maps
7.1
Conventions for Documenting Block Commands
7.2
(01h) OPERATION
7.3
(02h) ON_OFF_CONFIG
7.4
(03h) CLEAR_FAULTS
7.5
(04h) PHASE
7.6
(09h) P2_PLUS_WRITE
7.7
(0Ah) P2_PLUS_READ
7.8
(0Eh) PASSKEY
7.9
(10h) WRITE_PROTECT
7.10
(15h) STORE_USER_ALL
7.11
(16h) RESTORE_USER_ALL
7.12
(19h) CAPABILITY
7.13
(1Bh) SMBALERT_MASK
7.14
(20h) VOUT_MODE
7.15
(21h) VOUT_COMMAND
7.16
(22h) VOUT_TRIM
7.17
(24h) VOUT_MAX
7.18
(25h) VOUT_MARGIN_HIGH
7.19
(26h) VOUT_MARGIN_LOW
7.20
(27h) VOUT_TRANSITION_RATE
7.21
(29h) VOUT_SCALE_LOOP
7.22
(2Ah) VOUT_SCALE_MONITOR
7.23
(2Bh) VOUT_MIN
7.24
(33h) FREQUENCY_SWITCH
7.25
(35h) VIN_ON
7.26
(36h) VIN_OFF
7.27
(39h) IOUT_CAL_OFFSET
7.28
(40h) VOUT_OV_FAULT_LIMIT
7.29
(41h) VOUT_OV_FAULT_RESPONSE
7.30
(42h) VOUT_OV_WARN_LIMIT
7.31
(43h) VOUT_UV_WARN_LIMIT
7.32
(44h) VOUT_UV_FAULT_LIMIT
7.33
(45h) VOUT_UV_FAULT_RESPONSE
7.34
(46h) IOUT_OC_FAULT_LIMIT
7.35
(48h) IOUT_OC_LV_FAULT_LIMIT
7.36
(49h) IOUT_OC_LV_FAULT_RESPONSE
7.37
(4Ah) IOUT_OC_WARN_LIMIT
7.38
(4Fh) OT_FAULT_LIMIT
7.39
(50h) OT_FAULT_RESPONSE
7.40
(51h) OT_WARN_LIMIT
7.41
(55h) VIN_OV_FAULT_LIMIT
7.42
(60h) TON_DELAY
7.43
(61h) TON_RISE
7.44
(64h) TOFF_DELAY
7.45
(65h) TOFF_FALL
7.46
(78h) STATUS_BYTE
7.47
(79h) STATUS_WORD
7.48
(7Ah) STATUS_VOUT
7.49
(7Bh) STATUS_IOUT
7.50
(7Ch) STATUS_INPUT
7.51
(7Dh) STATUS_TEMPERATURE
7.52
(7Eh) STATUS_CML
7.53
(7Fh) STATUS_OTHER
7.54
(80h) STATUS_MFR_SPECIFIC
7.55
(88h) READ_VIN
7.56
(8Bh) READ_VOUT
7.57
(8Ch) READ_IOUT
7.58
(8Dh) READ_TEMPERATURE_1
7.59
(98h) PMBUS_REVISION
7.60
(99h) MFR_ID
7.61
(9Ah) MFR_MODEL
7.62
(9Bh) MFR_REVISION
7.63
(ADh) IC_DEVICE_ID
7.64
(AEh) IC_DEVICE_REV
7.65
(D1h) SYS_CFG_USER1
7.66
(D3h) PMBUS_ADDR
7.67
(D4h) COMP
7.68
(D5h) VBOOT_OFFSET_1
7.69
(D6h) STACK_CONFIG
7.70
(D8h) PIN_DETECT_OVERRIDE
7.71
(D9h) NVM_CHECKSUM
7.72
(DAh) READ_TELEMETRY
7.73
(DBh) STATUS_ALL
7.74
(DDh) EXT_WRITE_PROTECTION
7.75
(DEh) IMON_CAL
7.76
(FCh) FUSION_ID0
7.77
(FDh) FUSION_ID1
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Application
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.3.1
Input Capacitor Selection
8.2.3.2
Output Capacitor Selection
8.2.3.3
Compensation Selection
8.2.3.4
VOSNS and GOSNS Capacitor Selection
8.2.3.5
PMBus® Address Resistor Selection
8.2.4
Application Curves
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
8.4.2.1
Thermal Performance on EVM
9
Device and Documentation Support
9.1
Documentation Support
9.1.1
Related Documentation
9.2
Receiving Notification of Documentation Updates
9.3
Support Resources
9.4
Trademarks
9.5
Electrostatic Discharge Caution
9.6
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
1
Features
2.7V to 18V input voltage with external bias
4V to 18V input voltage without external bias
0.4V to 5.5V output voltage
Supports
25A
single-phase or 2 ×, 3 ×, or 4 × stacked configurations
Rds
on_HS
= 2.6mΩ, Rds
on_LS
= 1mΩ
400kHz to 2MHz operating frequency
(four discrete settings through pin-strap, additional settings through
PMBus®
)
PMBus programmable
Revision 1.5 compliant with
PASSKEY
security feature
Input voltage, output voltage, output current, temperature telemetry
Programmable overcurrent, overvoltage, undervoltage, overtemperature protections
Includes single command write function in stacked configuration
Extended write protection feature
Non-volatile memory to store configuration settings
Two methods for programming the output voltage
Internal resistor divider (discrete settings) with boot-up voltage selected by pin-strapping
External resistor divider (continuous settings) with boot-up voltage selected by VBOOT
Precision voltage reference and differential remote sense for high output accuracy
± 0.5% DAC accuracy from 0°C to 85°C junction
± 0.85% VOUT tolerance from –40°C to 125°C junction
Selectable FCCM/DCM in single phase only
Start-up without PMBus communication through pin-strapping
Safe start-up into prebiased output
0.5ms to 16ms programmable soft-start time
D-CAP4 control topology with fast transient response, supporting all ceramic output capacitors
Programmable internal loop compensation
Selectable cycle-by-cycle valley current limit
Open-drain power-good output