SLVSIN8 June   2026 TPSM65660

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Descriptions
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Internal LDO, VCC UVLO, and BIAS Input
      3. 7.3.3  Precision Enable and Adjustable Input Voltage UVLO (EN/UVLO)
      4. 7.3.4  Output Voltage Setpoint (FB, BIAS)
      5. 7.3.5  Adjustable Switching Frequency (RT)
      6. 7.3.6  Mode Selection and Clock Synchronization (MODE/SYNC)
        1. 7.3.6.1 Clock Synchronization
        2. 7.3.6.2 Clock Locking
      7. 7.3.7  Device Configuration (CNFG/SYNCOUT)
      8. 7.3.8  Dual Random Spread Spectrum (DRSS)
      9. 7.3.9  High-Side MOSFET Gate Drive (BST)
      10. 7.3.10 Soft Start and Recovery From Dropout
      11. 7.3.11 Protection Features
        1. 7.3.11.1 Power-Good Monitor
        2. 7.3.11.2 Overcurrent and Short-Circuit Protection
        3. 7.3.11.3 Hiccup-Mode Protection
        4. 7.3.11.4 Thermal Shutdown
      12. 7.3.12 Two-Phase, Single-Output Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Active Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Powertrain Components
        1. 8.1.1.1 Output Capacitors
        2. 8.1.1.2 Input Capacitors
        3. 8.1.1.3 EMI Filter
      2. 8.1.2 Error Amplifier and Compensation
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – 5V, 6A Synchronous Buck Regulator With Wide Input Voltage Range
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Choosing the Switching Frequency
          2. 8.2.1.2.2 Input Capacitor Selection
          3. 8.2.1.2.3 Output Capacitors
          4. 8.2.1.2.4 Output Voltage Setpoint
          5. 8.2.1.2.5 Compensation Components
          6. 8.2.1.2.6 Setting the Input Voltage UVLO
          7. 8.2.1.2.7 EMI Mitigation, RDRSS
          8. 8.2.1.2.8 Input Capacitor Selection
        3. 8.2.1.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Thermal Design and Layout
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
        1. 9.2.1.1 PCB Layout Resources
        2. 9.2.1.2 Thermal Design Resources
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information

Error Amplifier and Compensation

Figure 8-2 shows a Type-ll compensator using a transconductance error amplifier (EA). The dominant pole of the EA open-loop gain is set by the EA output resistance, ROEA, and effective bandwidth-limiting capacitance, CBW, as shown by Equation 18.

Equation 18. GEAopenloops = - gm×ROEA1+s×ROEA×CBW

The EA high-frequency pole is neglected in the above expression. Equation 19 expresses the compensator transfer function from output voltage to COMP, including the gain contribution from the feedback divider.

Equation 19. Gcs =v^c(s)v^out(s) = - VREFVOUT × gm×ROEA×1+sωz11+sωp1×1+sωp2

where

  • VREF is the feedback voltage reference
  • gm is the EA transconductance
  • ROEA is the EA output impedance
Equation 20. ωz1=1RCOMP×CCOMP
Equation 21. ωp1=1ROEA×CCOMP+CHF+CBW ≅1ROEA×CCOMP
Equation 22. ωp2=1RCOMP×CCOMP || CHF+CBW ≅1RCOMP×CHF

The EA compensation components create a pole close to the origin, a zero, and a high-frequency pole. Typically, RCOMP << ROEA and CCOMP >> CBW and CHF, so the approximations are valid. Figure 8-2 circles the poles in red and the zero in blue.

TPSM65660 Error
                    Amplifier and Compensation NetworkFigure 8-2 Error Amplifier and Compensation Network