SLVSJ01 June   2025 TXG8122-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions—TXG8122-Q1
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Electrical Characteristics
    5. 5.5  Supply Current Characteristics
    6. 5.6  Switching Characteristics, VCCA = 3.3 ± 0.3V
    7. 5.7  Switching Characteristics, VCCA = 5 ± 0.5V
    8. 5.8  Electrical Characteristics (85°C)
    9. 5.9  Supply Current Characteristics (85°C)
    10. 5.10 Switching Characteristics, VCCA = 3.3 ± 0.3V (85°C)
    11. 5.11 Switching Characteristics, VCCA = 5 ± 0.5V (85°C)
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Bidirectional Level Translation
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Regulatory Requirements
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Switching Characteristics, VCCA = 3.3 ± 0.3V

over recommended operating conditions, unless otherwise noted
PARAMETER Test Conditions Supply Voltage Side 2 (VCC2) UNIT
2.5 ± 0.25V 3.3 ± 0.3V 5.0 ± 0.5V
MIN TYP MAX MIN TYP MAX MIN TYP MAX
tf1 Output signal fall time (SDA1, SCL1) 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1,
R1 = 300Ω, C1 = 80pF		 21 21 21 ns
0.9 × VCC1 ≥ VO ≥ 900mV,
R1 = 300Ω, C1 = 80pF		 37 37 37 ns
tf2 Output signal fall time (SDA2, SCL2) 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2,
R2 = 260Ω, C2 = 550pF		 64 26 36 ns
0.9 × VCC2 ≥ VO ≥ 400mV,
R2 = 260Ω, C2 = 550pF		 51 75 159 ns
tr1 Output signal rise time (SDA1, SCL1) 0.7 × VCC1 ≥ VO ≥ 0.3 × VCC1,
R1 = 300Ω, C1 = 80pF		 22 22 22 ns
tr2 Output signal rise time (SDA2, SCL2) 0.7 × VCC2 ≥ VO ≥ 0.3 × VCC2,
R2 = 260Ω, C2 = 550pF		 104 104 104 ns
tpLH1-2 Low-to-high propagation delay, side 1 to side 2 VI = 535mV, VO = 0.7 × VCC2,
R1 = 300Ω, R2 = 260Ω,
C1 = 80pF, C2 = 550pF		 209 209 209 ns
tpHL1-2 High-to-low propagation delay, side 1 to side 2 VI = 550mV, VO = 0.7 × VCC2,
R1 = 300Ω, R2 = 260Ω,
C1 = 80pF, C2 = 550pF		 101 140 86 ns
tpLH2-1 Low-to-high propagation delay, side 2 to side 1 VI = 0.4 x VCC2, VO = 0.7 x VCC1,
R1 = 300Ω, R2 = 260 Ω,
C1 = 80pF, C2 = 550pF		 102 92 94 ns
tpHL2-1 High-to-low propagation delay, side 2 to side 1 VI = 0.4 x VCC2, VO = 0.3 × VCC1,
R1 = 300Ω, R2 = 260Ω,
C1 = 80pF, C2 = 550pF		 114 102 92 ns
PWD1-2 Pulse width distortion |tpHL1-2 – tpLH1-2| R1 = 300Ω, R2 = 260Ω,
C1 = 80pF, C2 = 550pF		 167 160 170 ns
PWD2-1 Pulse width distortion |tpHL2-1 – tpLH2-1| R1 = 300Ω, R2 = 260Ω,
C1 = 80pF, C2 = 550pF		 36 23.5 26 ns
tLOOP1 Round-trip propagation delay on side
1		 0.4V ≤ VI ≤ 0.3 × VCC1,
R1 = 300Ω, C1 = 80pF,
R2 = 260Ω, C2 = 550pF		 195 196 201 ns