SLVSJF4 October   2025 TPS7E66-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Power-Good (PG)
      4. 6.3.4 Adjustable Power-Good Delay Timer (DELAY)
      5. 6.3.5 Undervoltage Lockout
      6. 6.3.6 Thermal Shutdown
      7. 6.3.7 Foldback Current Limit
      8. 6.3.8 Power Limit
      9. 6.3.9 Output Pulldown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Device Feedback Resistor Selection
      2. 7.1.2 Recommended Capacitor Types
      3. 7.1.3 Input and Output Capacitor Selection
      4. 7.1.4 Reverse Current
      5. 7.1.5 Feed-Forward Capacitor
      6. 7.1.6 Dropout Voltage
      7. 7.1.7 Estimating Junction Temperature
      8. 7.1.8 Power Dissipation (PD)
      9. 7.1.9 Power Dissipation Versus Ambient Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Choose Feedback Resistors
      3. 7.2.3 Setting the Adjustable Power-Good Delay
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

7.1.5 Feed-Forward Capacitor

For the adjustable-voltage version device, a feed-forward capacitor (CFF) can be connected from the OUT pin to the FB pin. CFF improves transient, noise, and PSRR performance, but is not required for regulator stability. Recommended CFF values are listed in the Section 5.3 table. A higher capacitance CFF can be used; however, the start-up time increases. For a detailed description of CFF tradeoffs, see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application note.

CFF and R1 form a zero in the loop gain at frequency fZ, while CFF, R1, and R2 form a pole in the loop gain at frequency fP. CFF zero and pole frequencies can be calculated from the following equations:

Equation 5. fZ = 1 / (2 × π × CFF × R1)
Equation 6. fP = 1 / (2 × π × CFF × (R1 || R2))