SLVSJF4 October   2025 TPS7E66-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Enable (EN)
      2. 6.3.2 Dropout Voltage
      3. 6.3.3 Power-Good (PG)
      4. 6.3.4 Adjustable Power-Good Delay Timer (DELAY)
      5. 6.3.5 Undervoltage Lockout
      6. 6.3.6 Thermal Shutdown
      7. 6.3.7 Foldback Current Limit
      8. 6.3.8 Power Limit
      9. 6.3.9 Output Pulldown
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Device Feedback Resistor Selection
      2. 7.1.2 Recommended Capacitor Types
      3. 7.1.3 Input and Output Capacitor Selection
      4. 7.1.4 Reverse Current
      5. 7.1.5 Feed-Forward Capacitor
      6. 7.1.6 Dropout Voltage
      7. 7.1.7 Estimating Junction Temperature
      8. 7.1.8 Power Dissipation (PD)
      9. 7.1.9 Power Dissipation Versus Ambient Temperature
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Choose Feedback Resistors
      3. 7.2.3 Setting the Adjustable Power-Good Delay
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 Evaluation Module
        2. 8.1.1.2 Spice Models
      2. 8.1.2 Device Nomenclature
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Over operating junction temperature range (TJ = –40°C to +150°C), VIN = 3.0V or VIN = VOUT(nom) + 0.5V (whichever is greater), IOUT = 1mA, VEN = 2.0V, CIN = 1.0µF, COUT = 4.7µF, and PG pin pulled up-to VIN with 100kΩ, unless otherwise noted. Typical values are at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB Feedback voltage 1.2 V
VUVLO+ Rising input supply UVLO VIN rising 2.8 2.91 V
VUVLO- Falling input supply UVLO VIN falling 2.6 2.7 V
VUVLO(HYST) VUVLO hysteresis 100 mV
VOUT Output voltage VOUT + 1.0V ≤ VIN ≤ 40V, IOUT = 35mA, TJ = 25℃ –0.6 0.6 %
VOUT + 1.0V ≤ VIN ≤ 40V, IOUT = 35mA –1.2 1.0
1mA ≤ IOUT ≤ 150mA, 1.0V ≤ VIN – VOUT ≤ 25V –1.2 1.2
ΔVOUT(ΔVIN) Line regulation IOUT = 1mA, VOUT + 0.5V ≤ VIN ≤ 40V 6 mV
Δ%VOUT/ΔVIN 0.02 %/V
ΔVOUT(ΔIOUT) Load regulation 1mA ≤ IOUT ≤ 150mA, VIN = VOUT + 1.0V 15 mV
Δ%VOUT/ΔIOUT 0.75 %/A
VDO Dropout voltage IOUT = 150mA 0.45 0.825 V
IOUT = 150mA, for adjustable 0.45 0.9
VDO Dropout voltage IOUT = 100mA 0.3 0.55 V
IOUT = 100mA, for adjustable 0.28 0.6
ILIM Output current limit VOUT forced at 0.9 × VOUT(nom), VIN = VOUT(nom) + 1.0V 180 250 325 mA
ISC Short-circuit current limit RLOAD = 20 mΩ 10 28 55 mA
IPLIMIT Current limit at max headroom VIN = 40V, VOUT = 1.2V 15 mA
VHEADROOM Max headroom at full load VOUT = 1.2V 25 V
IFB Feedback current VIN = 40V -10 10 nA
IQ Quiescent current 3.0V ≤ VIN ≤ VOUT – 0.2V , IOUT = 0mA 12 25 µA
IOUT = 0mA 2.8 5.2
VOUT + 0.5V ≤ VIN ≤ 40V , IOUT = 0mA 7.6
IGND Ground current IOUT = 1mA 16.5 20 µA
IGND Ground current VIN = VOUT + 1.0V, IOUT = 150mA 350 µA
ISHUTDOWN Shutdown current VEN = 0V, TJ = 25℃ 0.45 µA
VOUT + 0.5V ≤ VIN ≤ 40V , VEN = 0V 1.25
Tstart-up Start-up time VIN, VEN tied together, VIN ramped to VOUT(nom) + 0.5V, IOUT = 0mA 500 µs
IEN EN pin current 0V ≤ VEN ≤ 40V, VIN and VEN tied together 0.5 µA
0V ≤ VIN ≤ 40V, VEN = 0V 0.5
VIL(EN) EN pin low-level input voltage (disable device) 0.5 V
VIH(EN) EN pin high-level input voltage (enable device) 1.1
VHYST(EN) EN pin hysteresis (enable device) 0.11 V
PSRR Power-supply ripple rejection VIN – VOUT = 2.0 V, IOUT = 150mA, f = 100kHz 45 dB
Vn Output noise voltage Bandwidth = 10Hz to 100kHz, VIN – VOUT = 2.0 V, IOUT = 150mA 650 µVRMS
VIT-(PG) Falling PG pin threshold For falling VOUT 85 90 94 %
VIT+(PG) Rising PG pin threshold For rising VOUT 90 93 96 %
VOL(PG) PG pin low-level output voltage VOUT < VIT-(PG), VIN = 3.0V, IPG = –1 mA (current into device) 0.4 V
Ilkg(PG) PG pin leakage current VOUT > VIT+(PG), VPG = 40V 0.01 1 µA
Delay(PG) PG pin delay time 125 µs
Deglitch(PG) PG pin deglitch time 125 µs
I(PGDL_CHG) PG delay capacitor charging current VPGDL = 63% of VPGDL (typ) 2.5 µA
V(PGDL_TH) PG delay threshold to release PG high 2.5 V
Tsd+ Thermal shutdown temperature increasing Shutdown, temperature increasing 163 °C
Tsd- Thermal shutdown temperature decreasing Reset, temperature decreasing 150 °C
RDischarge Output discharge resistance VIN = 3.0V, VEN = 0V, TJ = 25℃, IOUT = 1mA 750 Ω
ISINK Sink current on output VOUT = VOUT × 1.05, TJ = 25℃ 3 mA