SLVSJL6 June 2026 LM851772-Q1
ADVANCE INFORMATION
The LM851772-Q1 high-side and low-side gate drivers incorporate short propagation delays, frequency depended dead-time control, and low-impedance output stages capable of delivering large peak currents with very fast rise and fall times to facilitate rapid turn-on and turn-off transitions of the external power MOSFETs. Very high di/dt probably cause unacceptable ringing if the trace lengths are not well controlled. Minimization of stray or parasitic gate loop inductance is key to optimizing gate drive switching performance, whether the inductance is series gate inductance that resonates with MOSFET gate capacitance or common source inductance (common to gate and power loops) that provides a negative feedback component opposing the gate drive command, and thereby increasing MOSFET switching times.
Connections from the gate driver outputs, HO1 and HO2, to the respective gates of the high-side MOSFETs are necessary to be as short as possible to reduce series parasitic inductance. Route HO1 and HO2 and SW1 and SW2 gate traces as a differential pair from the device pin to the high-side MOSFET, taking advantage of flux cancellation by reducing the loop area.
Connections from gate driver outputs, LO1 and LO2, to the respective gates of the low-side MOSFETs are necessary to be as short as possible to reduce series parasitic inductance. Route LO1 and LO2, and PGND traces as a differential pair from the device pin to the low-side MOSFET, taking advantage of flux cancellation by reducing the loop area.
Minimize the current loop path from the VCC, HB1, and HB2 pins through the respective capacitors as these provide the high instantaneous current.