SLVSJL6 June   2026 LM851772-Q1

ADVANCE INFORMATION  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Buck-Boost Control Scheme
        1. 8.3.1.1 Buck Mode
        2. 8.3.1.2 Boost Mode
        3. 8.3.1.3 Buck-Boost Mode
      2. 8.3.2  Power Save Mode
      3. 8.3.3  Reference System
        1. 8.3.3.1 Power On Reset and nRST-PIN
      4. 8.3.4  Internal VCC Regulators
        1. 8.3.4.1 VCC1 Regulator
        2. 8.3.4.2 VCC2 Regulator
      5. 8.3.5  Enable and Undervoltage Lockout
        1. 8.3.5.1 UVLO
      6. 8.3.6  Error Amplifier and Control
        1. 8.3.6.1 Output Voltage Regulation
        2. 8.3.6.2 Output Voltage Feedback
        3. 8.3.6.3 Voltage Regulation Loop
        4. 8.3.6.4 Dynamic Voltage Scaling
      7. 8.3.7  Output Voltage Discharge
      8. 8.3.8  Peak Current Sensor
      9. 8.3.9  Short Circuit - Hiccup Protection
      10. 8.3.10 Current Monitor/Limiter
        1. 8.3.10.1 Overview
        2. 8.3.10.2 Output Current Limitation
        3. 8.3.10.3 Output Current Monitor
      11. 8.3.11 Oscillator Frequency Selection
      12. 8.3.12 Frequency Synchronization
      13. 8.3.13 Output Voltage Tracking
        1. 8.3.13.1 Analog Voltage Tracking
        2. 8.3.13.2 Digital Voltage Tracking
      14. 8.3.14 Slope Compensation
      15. 8.3.15 Configurable Soft Start
      16. 8.3.16 Drive Pin
      17. 8.3.17 Dual Random Spread Spectrum – DRSS
      18. 8.3.18 Gate Driver
      19. 8.3.19 Cable Drop Compensation (CDC)
      20. 8.3.20 CFG-Pin and R2D Interface
      21. 8.3.21 Advanced Monitoring Features
        1. 8.3.21.1  Overview
        2. 8.3.21.2  BUSY
        3. 8.3.21.3  OFF
        4. 8.3.21.4  VOUT
        5. 8.3.21.5  IOUT
        6. 8.3.21.6  INPUT
        7. 8.3.21.7  TEMPERATURE
        8. 8.3.21.8  CML
        9. 8.3.21.9  OTHER
        10. 8.3.21.10 ILIM_OP
        11. 8.3.21.11 nFLT/nINT Pin Output
        12. 8.3.21.12 Status Byte
      22. 8.3.22 Protection Features
        1. 8.3.22.1 Thermal Shutdown (TSD)
        2. 8.3.22.2 Overcurrent Protection
        3. 8.3.22.3 Output Overvoltage Protection 1 (OVP1)
        4. 8.3.22.4 Output Overvoltage Protection 2 (OVP2)
        5. 8.3.22.5 Input Voltage Protection (IVP)
        6. 8.3.22.6 Power Good
        7. 8.3.22.7 Boot-Strap Undervoltage Protection
        8. 8.3.22.8 Boot-strap Overvoltage Clamp
        9. 8.3.22.9 CRC - CHECK
    4. 8.4 Device Functional Modes
      1. 8.4.1 Overview
      2. 8.4.2 Logic State Description
    5. 8.5 Programming
      1. 8.5.1 I2C Bus Operation
      2. 8.5.2 Clock Stretching
      3. 8.5.3 Data Transfer Formats
      4. 8.5.4 Single READ From a Defined Register Address
      5. 8.5.5 Sequential READ Starting from a Defined Register Address
      6. 8.5.6 Single WRITE to a Defined Register Address
      7. 8.5.7 Sequential WRITE Starting at a Defined Register Address
  10. LM851772-Q1 Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1  Custom Design with WEBENCH Tools
        2. 10.2.2.2  Frequency
        3. 10.2.2.3  Feedback Divider
        4. 10.2.2.4  Inductor and Current Sense Resistor Selection
        5. 10.2.2.5  Output Capacitor
        6. 10.2.2.6  Input Capacitor
        7. 10.2.2.7  Slope Compensation
        8. 10.2.2.8  UVLO Divider
        9. 10.2.2.9  Soft-Start Capacitor
        10. 10.2.2.10 nRST and EN/UVLO Pull-up Resistor Selection
        11. 10.2.2.11 MOSFETs QH1 and QL1
        12. 10.2.2.12 MOSFETs QH2 and QL2
        13. 10.2.2.13 Loop Compensation
        14. 10.2.2.14 External Component Selection
      3. 10.2.3 Application Curves
    3. 10.3 USB-PD Source with Power Path
    4. 10.4 Parallel (Multiphase) Operation
    5. 10.5 Wireless Charging Supply
    6. 10.6 Power Supply Recommendations
    7. 10.7 Layout
      1. 10.7.1 Layout Guidelines
        1. 10.7.1.1 Power Stage Layout
        2. 10.7.1.2 Gate Driver Layout
        3. 10.7.1.3 Controller Layout
      2. 10.7.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information
    2.     132

MOSFETs QH2 and QL2

The output side MOSFETs QH2 (Q4) and QL2 (Q3) see the output voltage of 48V and additional transient spikes at SW2 during switching. Therefore, QH2 and QL2 need to be rated for 58V or more. The gate plateau voltages of the MOSFETs need to be smaller than the minimum input voltage of the converter, otherwise, the MOSFETs do not always fully enhance during start-up or overload conditions.

The power loss in QH2 in buck mode of operation is approximated by:

Equation 48. PCOND(QH2)=IOUT2× RDS,On(QH2)

The power loss in QL2 in the boost mode of operation consists of both conduction and switching loss components given by:

Equation 49. PCOND(QL2)=1-VINVOUT×IOUT×VOUTVIN2× RDS,On(QL2)

and, respectively:

Equation 50. PSWQL2=12×VOUT×IOUT×VOUTVIN×tr+tf×fSW

The rise (tr) and the fall (tf) times is obtained by the MOSFET data sheet information or measured in the lab. Typically, a MOSFET with smaller RDSON (lower conduction loss) has longer rise and fall times (larger switching loss).

The power loss in QH2 in the boost mode of operation is shown below:

Equation 51. PCOND(QH2)=VINVOUT×IOUT×VOUTVIN2×RDS,On(QH2)