SLVSJQ4 Data sheet

SLVSJQ4 May 2026 TMF0020

PRODUCTION DATA

5.6 Timing Requirements

Minimum and Maximum specifications apply from T_A of −10°C to 85°C. Typical specifications are at 25°C and V_PUP = 3.3V and 5V (unless otherwise noted).

			MIN	NOM	MAX	UNIT
I/O PIN: GENERAL DATA
t_STARTUP	Start-up time	Minimum time SDQ single-wire serial interface must be HIGH before device responds with a presence pulse		10		ms
t_REC	Recovery Time	Standard speed⁽¹⁾⁽²⁾	5			µs
t_REC	Recovery Time	Overdrive speed⁽¹⁾⁽²⁾	5			µs
t_REH	Rising-Edge Hold-Off Time	Standard speed⁽¹⁾⁽²⁾	0.5		5	µs
t_SLOT	Time Slot Duration	Standard speed⁽³⁾	65			µs
t_SLOT	Time Slot Duration	Overdrive speed⁽³⁾	11			µs
I/O PIN: SINGLE-WIRE RESET, PRESENCE-DETECT CYCLE
t_RSTL	Reset Low Time	Standard speed	480		550	µs
t_RSTL	Reset Low Time	Overdrive speed	48		80	µs
t_PDH	Presence-Detect High Pulse	Standard speed	15		60	µs
t_PDH	Presence-Detect High Pulse	Overdrive speed	2		6	µs
t_PDL	Presence-Detect Low Time	Standard speed	60		240	µs
t_PDL	Presence-Detect Low Time	Overdrive speed	8		24	µs
t_PDS	Presence-Detect Sample Time ⁽⁴⁾,⁽⁵⁾	Standard speed	60	70	75	µs
t_PDS	Presence-Detect Sample Time ⁽⁴⁾,⁽⁵⁾	Overdrive speed	6	8.7	10	µs
IO PIN: SINGLE-WIRE WRITE
t_W0L	Write-Zero Low Time	Standard speed⁽⁶⁾	60		120	µs
t_W0L	Write-Zero Low Time	Overdrive speed⁽⁶⁾	6		15.5	µs
t_W1L	Write-One Low Time	Standard speed⁽⁶⁾	1		15	µs
t_W1L	Write-One Low Time	Overdrive speed⁽⁶⁾	1		2	µs
IO PIN: SINGLE-WIRE READ
t_RL	Read Low Time	Standard speed⁽²⁾⁽⁷⁾	5		15 - t_RC	µs
t_RL	Read Low Time	Overdrive speed⁽²⁾⁽⁷⁾	1		2 - t_RC	µs
t_RDS	Read Sample Time ⁽⁸⁾	Standard speed⁽²⁾⁽⁷⁾	t_RL + t_RC		15	µs
t_RDS	Read Sample Time ⁽⁸⁾	Overdrive speed⁽²⁾⁽⁷⁾	t_RL + t_RC		3	µs
FRAM
NCY	Write/Erase Cycles (Endurance)⁽²⁾				1M	Cycles
t_PROG	Programming Time⁽²⁾	For all 20Kb of memory			1	ms
t_DR	Data Retention⁽⁹⁾	At 80°C		10		Years
t_DR	Data Retention⁽⁹⁾	At 85°C		7		Years

(1) Make sure the voltage on SDQ single-wire serial interface is less or equal to V_ILMAX at all times when the host is driving SDQ single-wire serial interface to a logic 0 level.

(2) Specified by design, characterization or simulation only. Not production tested.

(3) Defines maximum possible bit rate.

(4) Interval after t_RSTL during which a bus host can read logic 0 on SDQ single-wire serial interface if a TMF0020 is present. The presence detect pulse can be outside this interval, but is complete within 2ms after power-up. This behavior addresses the scenario where the one-wire device has been powered off (bus low) for a long time. Bus power is then applied. The device is allowed to malfunction, and generate a presence pulse that violates the presence timing specification. However, the abnormal condition is resolved typically within 10ms.

(5) System requirement.

(6) t_ε in Figure 6-18 and Figure 6-19 represents the time required for the pullup circuitry to raise the voltage on the SDQ single-wire serial interface pin from V_IL to V_TH. Hence the actual maximum duration for the host to pull the line low is t_W1LMAX + t_F – t_ε and t_W0LMAX + t_F – t_ε, respectively.

(7) t_RC in Figure 6-20 represents the time required for the pullup circuitry to raise the voltage on the SDQ single-wire serial interface pin from V_IL to the input-high threshold of the host device. Hence, the actual maximum duration for the host to pull the line low is t_RLMAX + t_F.

(8) Refers to the minimum time after which the recognition of negative edge is possible after V_TH has been reached on the preceding rising edge.

(9) Data retention time is degraded as T_A increases. Long-term storage at elevated temperatures is not recommended.