SLVSJQ4 May   2026 TMF0020

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Functional Tests
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 20480-Bit FRAM
      2. 6.3.2 FRAM Status Memory
      3. 6.3.3 Address Registers and Transfer Status
      4. 6.3.4 Writing Data to the FRAM
      5. 6.3.5 TMF0020 Device ID
      6. 6.3.6 Bus Termination
    4. 6.4 Device Functional Modes
      1. 6.4.1 Test Procedures for Functional Tests
        1. 6.4.1.1 Multiple Target Configurations
    5. 6.5 Programming
      1. 6.5.1 Serial Communication
      2. 6.5.2 Initialization
      3. 6.5.3 ROM Commands
        1. 6.5.3.1 READ ROM Command [33h]
        2. 6.5.3.2 MATCH ROM Command [55h]
        3. 6.5.3.3 SKIP ROM Command [CCh]
        4. 6.5.3.4 SEARCH ROM Command [F0h]
        5. 6.5.3.5 RESUME Command [A5h]
        6. 6.5.3.6 OVERDRIVE SKIP ROM Command [3Ch]
        7. 6.5.3.7 OVERDRIVE MATCH ROM Command [69h]
      4. 6.5.4 Memory Function Commands
        1. 6.5.4.1 Write Scratchpad Command [0Fh]
        2. 6.5.4.2 Read Scratchpad Command [AAh]
        3. 6.5.4.3 Copy Scratchpad [55h]
        4. 6.5.4.4 Read Memory [F0h]
        5. 6.5.4.5 Extended Read Memory [A5h]
        6. 6.5.4.6 Memory Command Flow Charts
      5. 6.5.5 SDQ single-wire serial interface Signaling
        1. 6.5.5.1 RESET and PRESENCE PULSE
        2. 6.5.5.2 Write-Read-Time Slots
      6. 6.5.6 IDLE
      7. 6.5.7 CRC Generation
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information
    2. 10.2 Tape and Reel Information

5.5 Electrical Characteristics

Minimum and Maximum specifications apply from TA of -10°C to 85°C. Typical specifications are at 25°C and VPUP = 3.3V and 5V (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
I/O PIN: GENERAL DATA
VPUPPull-up Voltage±5% variation

(3.3V - Standard speed only)

3.133.33.46V
4.7555.25V
RPUPPull-up Resistance(1)(2)(3)500Ω
CCABLECable Capacitance(4)(5)1.7nF
CIOInput Capacitance(6)(4)2000pF
ILInput Load Current(7)714µA
VILInput Low Voltage(8)0.5V
VOLOutput Low VoltageMeasured with RPUP = 500Ω,
VPUP = 3.3V		0.40.5V
Measured with RPUP = 500Ω,
VPUP = 5V		0.40.5V
VTLHigh-to-Low Switching threshold(4)(3)(9)VPUP = 3.3V0.841.72V
VPUP = 5V23V
VTHLow-to-High Switching Threshold(4)(3)(10)VPUP = 3.3V1.642.75V
VPUP = 5V3.24.3V
VHYSwitching Hysteresis(4)(3)(11)VPUP = 3.3V0.441.1V
VPUP = 5V0.91.3V
(1) Maximum allowable pull-up resistance is dependent on the number of devices connected and the recovery time. The specified value is assuming six devices are connected in the system and minimum recovery time.
(2) Resistance tolerance to be within 1% or less.
(3) VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, single-wire timing, and capacitive loading on SDQ single-wire serial interface pin. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY.
(4) Specified by design, characterization or simulation only. Not production tested.
(5) System requirement.
(6) Maximum Capacitance value represents the internal parasitic capacitance when VPUP is first applied. Once the parasitic charge storage capacitance is charged, normal logic transitions are not affected.
(7) Applicable when SDQ single-wire serial interface is HIGH (at VPUP) and the device is in idle mode (no digital activity or memory access). The numbers indicates the stand-by current consumption.
(8) The voltage on SDQ single-wire serial interface needs to be less or equal to VILMAX at all times the host is driving SDQ single-wire serial interface to a logic 0 level.
(9) Voltage below which, during a falling edge on SDQ single-wire serial interface, logic 0 is detected.
(10) Voltage above which, during a rising edge on SDQ single-wire serial interface, logic 1 is detected.
(11) After VTH is crossed during a rising edge on SDQ single-wire serial interface pin, the voltage on SDQ single-wire serial interface must drop by at least VHY to be detected as logic 0.