SLVSL49 July   2026 LM2903L-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions: Single TL331L-Q1
    2. 4.2 Pin Configuration: Dual LM2903L-Q1
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - Single
    5. 5.5 Thermal Information - Dual
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Outputs
        1. 6.4.1.1 Comparator Output
      2. 6.4.2 Output Latching
        1. 6.4.2.1 Clear (CLR) Input
        2. 6.4.2.2 Transparent Mode
        3. 6.4.2.3 Latch Behavior
      3. 6.4.3 Inputs
        1. 6.4.3.1 Fail-Safe Inputs and Input Voltage Range
        2. 6.4.3.2 Input Protection
        3. 6.4.3.3 Internal Hysteresis
        4. 6.4.3.4 Unused Inputs
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Basic Comparator Definitions
        1. 7.1.1.1 Operation
        2. 7.1.1.2 Propagation Delay
        3. 7.1.1.3 Overdrive Voltage
    2. 7.2 Typical Applications
      1. 7.2.1 Window Comparator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.4.2.3 Latch Behavior

After power-on, TI recommends that the CLR pin be toggeled low to reset the latch. With the CLR pin high, the latch is armed and latches low upon the first high-to-low output transition. The following is a summary of the latch operation.

When the CLR pin is held low, the output is in continuous "Transparent" mode (output follows inputs continuously with no latching).

TL331L-Q1 LM2903L-Q1 Latch Timing ExampleFigure 6-1 Latch Timing Example

* Latch disabled in "Transparent mode"

  1. IN- > IN+, CLR is low, output is low in transparent mode.
  2. CLR brought high and arms latch, IN– still greater than IN+, output remains low and immediately latches low.
  3. IN+ > IN–, but output remains low due to latch condition.
  4. CLR is brought low to clear latched output. During the time the CLR pin is low, the output is in transparent mode. IN+ > IN–, so output goes high in transparent mode
  5. CLR is brought high, disabling transparent mode and arming the latch. IN+ > IN–, output remains high.
  6. +IN crosses -IN, output goes low and latches low.
  7. IN+ > IN–, output remains latched low.
  8. IN- >IN+, output remains latched low.
  9. CLR brought low, clearing latch and enabling transparent mode.
  10. IN+ > IN–, output immediately goes high in transparent mode.
  11. IN– > IN+, output immediately goes low in transparent mode.
  12. IN+ > IN–, output immediately goes high in transparent mode.
  13. IN– > IN+, output immediately goes low in transparent mode.