SLVSL49 July   2026 LM2903L-Q1

ADVMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1. 4.1 Pin Functions: Single TL331L-Q1
    2. 4.2 Pin Configuration: Dual LM2903L-Q1
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information - Single
    5. 5.5 Thermal Information - Dual
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Outputs
        1. 6.4.1.1 Comparator Output
      2. 6.4.2 Output Latching
        1. 6.4.2.1 Clear (CLR) Input
        2. 6.4.2.2 Transparent Mode
        3. 6.4.2.3 Latch Behavior
      3. 6.4.3 Inputs
        1. 6.4.3.1 Fail-Safe Inputs and Input Voltage Range
        2. 6.4.3.2 Input Protection
        3. 6.4.3.3 Internal Hysteresis
        4. 6.4.3.4 Unused Inputs
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Basic Comparator Definitions
        1. 7.1.1.1 Operation
        2. 7.1.1.2 Propagation Delay
        3. 7.1.1.3 Overdrive Voltage
    2. 7.2 Typical Applications
      1. 7.2.1 Window Comparator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.7 Switching Characteristics

VS = 5V, CLR = 5VPP, VO_PULLUP=5V, VCM = VS/2, CL = 15pF, RL = 5.1k Ohm, TA = 25°C (Unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
TPD-HL Propagation delay time, high-to-low TTL input Delay from mid-point of input to mid-point of output, RP = 5.1kΩ 300 ns
TPD-HL Propagation delay time, high-to-low Input overdrive = 5mV, Input step = 100mV from mid-point of input to mid-point of output, RP = 5.1kΩ 1000 ns
TPD-CLR-F Clear Fall to Latch Reset propagation delay time CLR = 1.8V to 5V, VID = 100mV,
RP = 5.1kΩ Delay from CLR falling edge signal to normal output HIGH condition (RP to Vpull-up)		 650 ns
CLR_Min_Pulse_Width Minimum Clear Hold Pulse time to register latch disable and transition output state CLR = 1.8V to 5V, VID= +100 mV
Minimum CLR pulse size required to register a change of state (latch reset) upon CLR falling edge		 70 ns
TFALL 5V Output Fall Time, 80% to 20% VID = –100mV
 		 20 ns
POWER ON TIME