SLVSL93A March   2026  – April 2026 UCC34141

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Electrical Characteristics
    7. 6.7 Safety Limiting Values
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-COM Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 COM-VEE Output Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and Power-Good
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Undervoltage Protection
        4. 7.3.4.4 Output Overvoltage Protection
        5. 7.3.4.5 Output Short Circuit Protection
        6. 7.3.4.6 Over-Temperature Protection
        7. 7.3.4.7 BSW Pin Faults Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD-COM Voltage Regulation
        2. 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.5.1 Layout Guidelines

The UCC34141 integrated isolated power solution simplifies system design and reduces board area usage. Follow these guidelines for proper PCB layout to achieve optimum performance. A minimum of 4-layer PCB layer stack using 2-ounce copper on external layers is recommended to accomplish a good thermal PCB design. It is not recommended to route signal tracks or place components directly beneath the UCC34141.

  1. Input capacitors between VIN pin and GNDP pin:
    1. Place the 0.1μF high frequency bypass capacitor (C3) as close as possible to pins 3, 4 (VIN) and pins 5–8 (GNDP) and on the same side of the PCB as the IC. 0402 ceramic SMD or smaller is a desired size for optimal placement. The self-resonant frequency in a range from 10MHz to 30MHz is most ideal to offer low impedance decoupling for the switching frequency noise of the internal isolated convertor. Do not place any vias between the bypass capacitor and the IC pins so as to force the high frequency current through the capacitor.
    2. Place the bulk VIN capacitor(s) (C2) as close as possible and parallel to the 0.1μF high frequency bypass capacitor (C3) and on the same side of the PCB as the IC as shown in Figure 8-5.
  2. Output capacitors between VDD pin and COM pin:
    1. Place the 0.1μF high frequency bypass capacitor (C5) as close as possible to pin 12 (VDD) and pins 10, 11 (COM) and on the same side of the PCB as the IC. 0402 ceramic SMD or smaller is a desired size for optimal placement. The self-resonant frequency in a range between 10MHz to 30MHz is most ideal to offer low impedance decoupling for the switching frequency noise of the internal isolated convertor. Do not place any vias between the bypass capacitor and the IC pins so as to force the high frequency current through the capacitor.
    2. Place the bulk VDD-COM capacitor (C8) as close as possible and parallel to the 0.1μF high frequency bypass capacitor (C5) and on the same side of the PCB as the IC as shown in Figure 8-5.
  3. Output capacitors between VEE pin and COM pin:
    1. Place the 2.2μF high frequency bypass capacitor (C9) as close as possible to VEE and COM pins. The self-resonant frequency in 3MHz to 4MHz is most ideal to offer low impedance decoupling for the switching frequency noise of the buck-boost converter with the 3.3uH inductor (L1) selection. It is possible to put the capacitor on the different side of PCB and use vias to connect, to reduce the switching loop between the capacitor and the internal low-side MOSFET of the VEE buck-boost converter. In addition, putting the capacitor on different side also simplifies the decoupling capacitor placement of VDD pin and COM pin. An example of bottom side PCB placement of C9 and L1 is shown in Figure 8-9.
  4. Feedback:
    1. COMA must be isolated through all PCB layers, from the COM plane. Use one via to make a direct connection to the low-side resistor and filter capacitor from FBVDD pin, same as the low-side filter capacitor from FBVEE pin.
    2. Place the RFBVDD feedback resistors (R6 and R7) and the decoupling ceramic capacitor (C6) close to the IC.
    3. The top-side feedback resistor must be placed next to the low-side resistor with a short, direct connection between both resistors and single connection to FBVDD pin. The top connection to sense the regulated rail (VDD-COM) must be routed and connected at the VDD bias capacitor remote location near the gate driver pins for best accuracy and best transient response.
    4. The VEE feedback resistor (R5) must be placed with the decoupling ceramic capacitor (C4) next to FBVEE (pin 15); while the connection to sense the regulated rail (COM-VEE) must be routed and connected at the COM bias capacitor remote location near the gate driver pins for best accuracy and best transient response.
    5. When using the dual output mode, the buck-boost inductor (L1) and a 2.2uF decoupling ceramic capacitor (C9) must be populated. They can be place on the opposite side of the IC or on the same layer as IC.
    6. A layout example is shown in Figure 8-6, where L2 (yellow) is routed on layer 2 and L3 (green) is routed on layer 3.
  5. Thermal vias: The UCC34141 internal transformer makes a direct connection to the lead frame. It is therefore critical to provide adequate space and proper heat-sinking designed into the PCB as outlined in the steps below.
    1. TI recommends to connect the VIN, GNDP, VDD, and COM pins to internal ground or power planes through multiple vias. Alternatively, make the polygons connected to these pins as wide as possible.
    2. Use multiple thermal vias connecting PCB top side GNDP copper to bottom side GNDP copper. If possible, it is recommended to use 2-ounce copper on external top and bottom PCB layers.
    3. Use multiple thermal vias connecting PCB top side VEE copper to bottom side VEE copper. If possible, it is recommended to use 2-ounce copper on external top and bottom PCB layers.
    4. Thermal vias connecting top and bottom copper can also connect to internal copper layers for further improved heat extraction.
    5. Thermal vias must be similar to pattern shown below but apply as many as the copper area allows. TI recommends to use thermal via with 30mil diameter, 12mil hole size.
    6. A layout example is shown in Figure 8-7. For cases where less copper area is available, use as many thermal vias as the design permits, placed close to pins 5-8 (primary) and 9-11 (secondary).
  6. Creepage clearance: To maintain the full creepage, clearance and voltage isolation ratings specified in the data sheet, avoid routing signal traces or placing components directly under the UCC34141. Maintain the clearance width highlighted in red, throughout the entire defined isolation barrier. Keep-out clearance for basic isolation can be 50% less than the reinforced isolation requirement (8.2mm). Using 8.2mm provides additional margin. A layout example is shown in Figure 8-8.
  7. Gate driver output capacitors: CVDD_GD (C11 and C12) and CVEE_GD (C10) are reference designators referred to in the UCC34141 calculator tool. C11 and C12 are the capacitors between VDD-COM and C10 is the capacitor between COM-VEE. C10-12 are capacitors required by the gate driver IC.
    1. CVDD_GD and CVEE_GD must be placed next to the gate driver IC for best decoupling and gate driver switching performance.
    2. For optimal voltage regulation, the feedback trace from VEE (FBVEE) and VDD (FBVDD) must be as direct as possible so that the voltage feedback is being sensed directly at the VDD and VEE capacitors near the gate driver IC.
  8. Power good pins decoupling capacitor: The decoupling capacitor must be placed close to pin 2 (power good pin) and on the same side of the PCB as the UCC34141. Refer to C13 placement shown in Figure 8-5.