SLVSL93A March   2026  – April 2026 UCC34141

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Insulation Specifications
    6. 6.6 Electrical Characteristics
    7. 6.7 Safety Limiting Values
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Stage Operation
        1. 7.3.1.1 VDD-COM Voltage Regulation
        2. 7.3.1.2 COM-VEE Voltage Regulation
        3. 7.3.1.3 COM-VEE Output Capability
      2. 7.3.2 Output Voltage Soft Start
      3. 7.3.3 ENA and Power-Good
      4. 7.3.4 Protection Functions
        1. 7.3.4.1 Input Undervoltage Lockout
        2. 7.3.4.2 Input Overvoltage Lockout
        3. 7.3.4.3 Output Undervoltage Protection
        4. 7.3.4.4 Output Overvoltage Protection
        5. 7.3.4.5 Output Short Circuit Protection
        6. 7.3.4.6 Over-Temperature Protection
        7. 7.3.4.7 BSW Pin Faults Protection
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 VDD-COM Voltage Regulation
        2. 8.2.2.2 COM-VEE Voltage Regulation and Single Output Configuration
    3. 8.3 System Examples
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Third-Party Products Disclaimer
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

7.3.1.1 VDD-COM Voltage Regulation

The VDD output is the main output of the module. The power stage operation is controlled by a hysteretic comparator that detects when the FBVDD pin voltage is above or below the internal reference voltage VFBVDD_REF. The FBVDD voltage is by the voltage divider between RFBVDD_TOP and RFBVDD_BOT. When FBVDD voltage stays below the turn-off threshold, the power stage operates in burst on state, delivering power to the secondary side and the VDD voltage increases. After FBVDD reaches the turn-off threshold, the power stage turns off. With the power stage off the VDD output capacitors supply the load, and VDD drops. After FBVDD voltage drops below the turn-on threshold, the power stage is turned on again. With the accurate voltage reference and hysteresis control, the VDD output voltage can be regulated with an accuracy of VVDD_REG.

To improve the noise immunity, a small capacitor CFBVDD of 220pF must be added between FBVDD and COMA pins. In an environment with high electro-magnetic noise, higher feedback decoupling capacitance CFBVDD, and lower feedback resistance RFBVDD_TOP and RFBVDD_BOT values can be selected to further improve the noise immunity of the VDD feedback loop.

UCC34141 VDD-COM Voltage Regulation Functional Block DiagramFigure 7-1 VDD-COM Voltage Regulation Functional Block Diagram
UCC34141 Concept of VDD-COM Regulation Scheme Figure 7-2 Concept of VDD-COM Regulation Scheme