SLVSLM6 May   2026 BQ76972-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76972-Q1
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 REG2 LDO
    14. 6.14 Voltage References
    15. 6.15 Coulomb Counter
    16. 6.16 Coulomb Counter Digital Filter (CC1)
    17. 6.17 Current Measurement Digital Filter (CC2)
    18. 6.18 Current Wake Detector
    19. 6.19 Analog-to-Digital Converter
    20. 6.20 Cell Voltage Measurement Accuracy
    21. 6.21 Multifunction Pin ADC Measurement
    22. 6.22 Cell Balancing
    23. 6.23 Cell Open Wire Detector
    24. 6.24 Internal Temperature Sensor
    25. 6.25 Thermistor Measurement
    26. 6.26 Internal Oscillators
    27. 6.27 High-side NFET Drivers
    28. 6.28 Comparator-Based Protection Subsystem
    29. 6.29 Timing Requirements - I2C Interface, 100kHz Mode
    30. 6.30 Timing Requirements - I2C Interface, 400kHz Mode
    31. 6.31 Timing Requirements - HDQ Interface
    32. 6.32 Timing Requirements - SPI Interface
    33. 6.33 Interface Timing Diagrams
    34. 6.34 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Usage of VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Cell Voltage Measurement Accuracy
        1. 7.5.8.1 Cell Offset Calibration
      9. 7.5.9  Voltage Calibration (ADC Measurements)
      10. 7.5.10 Voltage Calibration (COV and CUV Protections)
      11. 7.5.11 Current Calibration
      12. 7.5.12 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 and REG2 LDO Controls
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  DDSG and DCHG Pin Operation
      10. 7.7.10 Fuse Drive
      11. 7.7.11 Cell Open Wire
      12. 7.7.12 Low Frequency Oscillator
      13. 7.7.13 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 SPI Communications
        1. 7.9.3.1 SPI Protocol
      4. 7.9.4 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
    7. 8.7 Power Supply Requirements
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, Orderable Information

8.6 Unused Pins

Some device pins might not be needed in a particular application. The manner in which each must be terminated in this case is described below.

Table 8-3 Terminating Unused Pins
Pin Name Recommendation
1–16, 48 VC0–VC16 Cell inputs 1, 2, and 16 must always be connected to actual cells, with cells connected between VC1 and VC0, VC2 and VC1, and VC16 and VC15. VC0 must be connected through a resistor and capacitor on the pcb to pin 17 (VSS). Pins related to unused cells (which can be cell 3–cell 15, pins 1–13) can be connected to the cell stack to measure interconnect resistance or provide a Kelvin-connection to actual cells, in which case they must include a series resistor and parallel capacitor, in similar fashion to pins connected to actual cells (see Usage of VC Pins for Cells Versus Interconnect). Another option is to short unused VC pins directly to an adjacent VC pin. All VC pins must be connected to either an adjacent VC pin, an actual cell (through R and C) or stack interconnect resistance (through R and C).
18, 20 SRP, SRN If not used, these pins must be connected to pin 17 (VSS).
19, 44 NC These pins are not connected to silicon. They can be left floating or connected to an adjacent pin or connected to VSS.
21, 23, 25, 28, 29, 30, 31, 32 TS1, TS3, ALERT, HDQ, CFETOFF, DFETOFF, DCHG, DDSG If not used, these pins can be left floating or connected to pin 17 (VSS). Any of these pins (except for TS1 and TS3) can be configured with the internal weak pulldown resistance enabled during operation, although this is not necessary.
22 TS2 If the device is intended to enter SHUTDOWN mode, the TS2 pin must be left floating. If SHUTDOWN mode is not used in the application, and the TS2 pin is not used for a thermistor or ADCIN measurement, the TS2 pin can be left floating or connected to pin 17 (VSS).
33 RST_SHUT If not used, this pin must be connected to pin 17 (VSS).
34, 35 REG1, REG2 If not used, these pins can be left floating or connected to pin 17 (VSS).
36 REGIN If not used, this pin must be connected to pin 17 (VSS).
37 BREG If this pin is not used and pin 36 (REGIN) is also not used, both pins must be connected to pin 17 (VSS). If this pin is not used but pin 36 is used (such as driven from an external source), then this pin must be connected to pin 36 (REGIN).
38 FUSE If not used, this pin can be left floating or connected to pin 17 (VSS).
39 PDSG If not used, this pin must be left floating.
40 PCHG If not used, this pin must be left floating.
41 LD If the DSG driver does not be used, this pin can be connected through a series resistor to the PACK+ connector, or can be connected to pin 17 (VSS).
43 DSG If not used, this pin must be left floating.
45 CHG If not used, this pin must be left floating.
46 CP1 If not used, this pin must be connected to pin 47 (BAT).
Note: If the charge pump is enabled with CP1 connected to BAT, the device will consume an additional approx. 200µA.