SLVSLM6 May   2026 BQ76972-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76972-Q1
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 REG2 LDO
    14. 6.14 Voltage References
    15. 6.15 Coulomb Counter
    16. 6.16 Coulomb Counter Digital Filter (CC1)
    17. 6.17 Current Measurement Digital Filter (CC2)
    18. 6.18 Current Wake Detector
    19. 6.19 Analog-to-Digital Converter
    20. 6.20 Cell Voltage Measurement Accuracy
    21. 6.21 Multifunction Pin ADC Measurement
    22. 6.22 Cell Balancing
    23. 6.23 Cell Open Wire Detector
    24. 6.24 Internal Temperature Sensor
    25. 6.25 Thermistor Measurement
    26. 6.26 Internal Oscillators
    27. 6.27 High-side NFET Drivers
    28. 6.28 Comparator-Based Protection Subsystem
    29. 6.29 Timing Requirements - I2C Interface, 100kHz Mode
    30. 6.30 Timing Requirements - I2C Interface, 400kHz Mode
    31. 6.31 Timing Requirements - HDQ Interface
    32. 6.32 Timing Requirements - SPI Interface
    33. 6.33 Interface Timing Diagrams
    34. 6.34 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Usage of VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Cell Voltage Measurement Accuracy
        1. 7.5.8.1 Cell Offset Calibration
      9. 7.5.9  Voltage Calibration (ADC Measurements)
      10. 7.5.10 Voltage Calibration (COV and CUV Protections)
      11. 7.5.11 Current Calibration
      12. 7.5.12 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 and REG2 LDO Controls
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  DDSG and DCHG Pin Operation
      10. 7.7.10 Fuse Drive
      11. 7.7.11 Cell Open Wire
      12. 7.7.12 Low Frequency Oscillator
      13. 7.7.13 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 SPI Communications
        1. 7.9.3.1 SPI Protocol
      4. 7.9.4 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
    7. 8.7 Power Supply Requirements
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, Orderable Information

7.5.3 Coulomb Counter and Digital Filters

The BQ76972-Q1 device monitors pack current using a low-side sense resistor, which connects to the SRP and SRN pins through an external RC filter, which must be connected such that a charging current will create a positive voltage on SRP relative to SRN. The differential voltage between SRP and SRN is digitized by an integrated coulomb counter ADC, which can digitize voltages over a ±200 mV range and uses multiple digital filters to provide optimized measurement of the instantaneous, averaged, and integrated current. The device supports a wide range of sense resistor value, with a larger value providing better resolution for the digitized result. The maximum value of sense resistor must be limited to ensure the differential voltage remains within the ±200mV range for system operation when current measurement is desired. For example, a system with maximum discharge current of 200A during normal operation (not a fault condition) must limit the sense resistor to 1mΩ or below.

The SRP and SRN pins can also support higher positive voltages relative to VSS, which can occur during overcurrent or short circuit in discharge conditions, without damage to the device, although the current is not accurately digitized in this case. For example, a system with a 1mΩ sense resistor and the Short Circuit in Discharge protection threshold programmed to a 500mV level can trigger an SCD protection fault when a discharge current of 500A is detected.

Multiple digitized current values are available for readout over the serial communications interface, including two using separate hardware digital filters, CC1 and CC2, as well as a firmware filter CC3.

The CC1 filter generates a 16-bit current measurement that is used for charge integration and other decision purposes, with one output generated every 250ms when the device is operating in NORMAL mode.

The CC2 filter generates a 24-bit current measurement that is used for current reporting, with one output every 3ms when the device is operating in NORMAL mode (which can be reduced to one output every 1.5ms based on setting, with reduced measurement resolution). It is reported in 16-bit format, and the 24-bit CC2 data is also available as raw coulomb counter ADC counts, provided in a 32-bit format (with the data contained in the lower 24-bits and the upper 8-bits sign-extended).

The CC3 filter output is an average of a programmable number of CC2 current samples (up to 255), based on the configuration setting. The CC3 output is reported in 32-bit format.

The integrated passed charge is available as a 64-bit value, which includes the upper 32-bits of accumulated charge as the integer portion, the lower 32-bits of accumulated charge as the fractional portion, and a 32-bit accumulated time over which the charge has been integrated in units of seconds. The accumulated charge integration and timer can be reset by a command from the host over the digital communications interface.