SLVSLM6 May   2026 BQ76972-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76972-Q1
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 REG2 LDO
    14. 6.14 Voltage References
    15. 6.15 Coulomb Counter
    16. 6.16 Coulomb Counter Digital Filter (CC1)
    17. 6.17 Current Measurement Digital Filter (CC2)
    18. 6.18 Current Wake Detector
    19. 6.19 Analog-to-Digital Converter
    20. 6.20 Cell Voltage Measurement Accuracy
    21. 6.21 Multifunction Pin ADC Measurement
    22. 6.22 Cell Balancing
    23. 6.23 Cell Open Wire Detector
    24. 6.24 Internal Temperature Sensor
    25. 6.25 Thermistor Measurement
    26. 6.26 Internal Oscillators
    27. 6.27 High-side NFET Drivers
    28. 6.28 Comparator-Based Protection Subsystem
    29. 6.29 Timing Requirements - I2C Interface, 100kHz Mode
    30. 6.30 Timing Requirements - I2C Interface, 400kHz Mode
    31. 6.31 Timing Requirements - HDQ Interface
    32. 6.32 Timing Requirements - SPI Interface
    33. 6.33 Interface Timing Diagrams
    34. 6.34 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  Diagnostics
    4. 7.4  Device Configuration
      1. 7.4.1 Commands and Subcommands
      2. 7.4.2 Configuration Using OTP or Registers
      3. 7.4.3 Device Security
      4. 7.4.4 Scratchpad Memory
    5. 7.5  Measurement Subsystem
      1. 7.5.1  Voltage Measurement
        1. 7.5.1.1 Voltage Measurement Schedule
        2. 7.5.1.2 Usage of VC Pins for Cells Versus Interconnect
        3. 7.5.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.5.2  General Purpose ADCIN Functionality
      3. 7.5.3  Coulomb Counter and Digital Filters
      4. 7.5.4  Synchronized Voltage and Current Measurement
      5. 7.5.5  Internal Temperature Measurement
      6. 7.5.6  Thermistor Temperature Measurement
      7. 7.5.7  Factory Trim of Voltage ADC
      8. 7.5.8  Cell Voltage Measurement Accuracy
        1. 7.5.8.1 Cell Offset Calibration
      9. 7.5.9  Voltage Calibration (ADC Measurements)
      10. 7.5.10 Voltage Calibration (COV and CUV Protections)
      11. 7.5.11 Current Calibration
      12. 7.5.12 Temperature Calibration
    6. 7.6  Primary and Secondary Protection Subsystems
      1. 7.6.1 Protections Overview
      2. 7.6.2 Primary Protections
      3. 7.6.3 Secondary Protections
      4. 7.6.4 High-Side NFET Drivers
      5. 7.6.5 Protection FETs Configuration and Control
        1. 7.6.5.1 FET Configuration
        2. 7.6.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.6.6 Load Detect Functionality
    7. 7.7  Device Hardware Features
      1. 7.7.1  Voltage References
      2. 7.7.2  ADC Multiplexer
      3. 7.7.3  LDOs
        1. 7.7.3.1 Preregulator Control
        2. 7.7.3.2 REG1 and REG2 LDO Controls
      4. 7.7.4  Standalone Versus Host Interface
      5. 7.7.5  Multifunction Pin Controls
      6. 7.7.6  RST_SHUT Pin Operation
      7. 7.7.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.7.8  ALERT Pin Operation
      9. 7.7.9  DDSG and DCHG Pin Operation
      10. 7.7.10 Fuse Drive
      11. 7.7.11 Cell Open Wire
      12. 7.7.12 Low Frequency Oscillator
      13. 7.7.13 High Frequency Oscillator
    8. 7.8  Device Functional Modes
      1. 7.8.1 Overview
      2. 7.8.2 NORMAL Mode
      3. 7.8.3 SLEEP Mode
      4. 7.8.4 DEEPSLEEP Mode
      5. 7.8.5 SHUTDOWN Mode
      6. 7.8.6 CONFIG_UPDATE Mode
    9. 7.9  Serial Communications Interface
      1. 7.9.1 Serial Communications Overview
      2. 7.9.2 I2C Communications
      3. 7.9.3 SPI Communications
        1. 7.9.3.1 SPI Protocol
      4. 7.9.4 HDQ Communications
    10. 7.10 Cell Balancing
      1. 7.10.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
    7. 8.7 Power Supply Requirements
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, Orderable Information

5 Pin Configuration and Functions

BQ76972-Q1
Table 5-1 BQ76972-Q1 TQFP Package (PFB) Pin Functions
PIN I/O TYPE DESCRIPTION
NO. NAME
1 VC15 I IA Sense voltage input pin for the fifteenth cell from the bottom of the stack, balance current input for the fifteenth cell from the bottom of the stack, and return balance current for the sixteenth cell from the bottom of stack
2 VC14 I IA Sense voltage input pin for the fourteenth cell from the bottom of the stack, balance current input for the fourteenth cell from the bottom of the stack, and return balance current for the fifteenth cell from the bottom of the stack
3 VC13 I IA Sense voltage input pin for the thirteenth cell from the bottom of the stack, balance current input for the thirteenth cell from the bottom of the stack, and return balance current for the fourteenth cell from the bottom of the stack
4 VC12 I IA Sense voltage input pin for the twelfth cell from the bottom of the stack, balance current input for the twelfth cell from the bottom of the stack, and return balance current for the thirteenth cell from the bottom of the stack
5 VC11 I IA Sense voltage input pin for the eleventh cell from the bottom of the stack, balance current input for the eleventh cell from the bottom of the stack, and return balance current for the twelfth cell from the bottom of the stack
6 VC10 I IA Sense voltage input pin for the tenth cell from the bottom of the stack, balance current input for the tenth cell from the bottom of the stack, and return balance current for the eleventh cell from the bottom of the stack
7 VC9 I IA Sense voltage input pin for the ninth cell from the bottom of the stack, balance current input for the ninth cell from the bottom of the stack, and return balance current for the tenth cell from the bottom of the stack
8 VC8 I IA Sense voltage input pin for the eighth cell from the bottom of the stack, balance current input for the eighth cell from the bottom of the stack, and return balance current for the ninth cell from the bottom of the stack
9 VC7 I IA Sense voltage input pin for the seventh cell from the bottom of the stack, balance current input for the seventh cell from the bottom of the stack, and return balance current for the eighth cell from the bottom of the stack
10 VC6 I IA Sense voltage input pin for the sixth cell from the bottom of the stack, balance current input for the sixth cell from the bottom of the stack, and return balance current for the seventh cell from the bottom of the stack
11 VC5 I IA Sense voltage input pin for the fifth cell from the bottom of the stack, balance current input for the fifth cell from the bottom of the stack, and return balance current for the sixth cell from the bottom of the stack
12 VC4 I IA Sense voltage input pin for the fourth cell from the bottom of the stack, balance current input for the fourth cell from the bottom of the stack, and return balance current for the fifth cell from the bottom of the stack
13 VC3 I IA Sense voltage input pin for the third cell from the bottom of the stack, balance current input for the third cell from the bottom of the stack, and return balance current for the fourth cell from the bottom of the stack
14 VC2 I IA Sense voltage input pin for the second cell from the bottom of the stack, balance current input for the second cell from the bottom of the stack, and return balance current for the third cell from the bottom of the stack
15 VC1 I IA Sense voltage input pin for the first cell from the bottom of the stack, balance current input for the first cell from the bottom of the stack, and return balance current for the second cell from the bottom of the stack
16 VC0 I IA Sense voltage input pin for the negative terminal of the first cell from the bottom of the stack, and return balance current for the first cell from the bottom of the stack
17 VSS — P Device ground
18 SRP I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRP is the top of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
19 NC — — This pin is not connected to silicon.
20 SRN I IA Analog input pin connected to the internal coulomb counter peripheral for integrating a small voltage between SRP and SRN, where SRN is the bottom of the sense resistor. A charging current generates a positive voltage at SRP relative to SRN.
21 TS1 I/O OD, I/OA Thermistor input, or general purpose ADC input
22 TS2 I/O OD, I/OA Thermistor input and functions as wakeup from SHUTDOWN, or general purpose ADC input
23 TS3 I/O OD, I/OA Thermistor input, or general purpose ADC input
24 REG18 O P Internal 1.8V LDO output (only for internal use)
25 ALERT I/O I/OD, I/OA Multifunction pin, can be ALERT output, or HDQ I/O, or thermistor input, or general purpose ADC input, or general purpose digital output
26 SCL I/O I/OD Multifunction pin, can be SCL or SPI_SCLK
27 SDA I/O I/OD Multifunction pin, can be SDA or SPI_MISO
28 HDQ I/O I/OD, I/OA Multifunction pin, can be HDQ I/O, SPI_MOSI, thermistor input, general purpose ADC input, or general purpose digital output
29 CFETOFF I/O I/OD, I/OA Multifunction pin, can be CFETOFF, SPI_CS, thermistor input, general purpose ADC input, or general purpose digital output
30 DFETOFF I/O I/OD, I/OA Multifunction pin, can be DFETOFF, BOTHOFF, thermistor input, general purpose ADC input, or general purpose digital output
31 DCHG I/O OD, I/OA Multifunction pin, can be DCHG, thermistor input, general purpose ADC input, or general purpose digital output
32 DDSG I/O OD, I/OA Multifunction pin, can be DDSG, thermistor input, general purpose ADC input, or general purpose digital output
33 RST_SHUT I ID Digital input pin for reset or shutdown
34 REG2 O P Second LDO (REG2) output, which can be programmed for 1.8V, 2.5V, 3.0V, 3.3V, or 5.0V.
35 REG1 O P First LDO (REG1) output, which can be programmed for 1.8V, 2.5V, 3.0V, 3.3V, or 5.0V.
36 REGIN I IA Input pin for REG1 and REG2 LDOs
37 BREG O OA Base control signal for external preregulator transistor
38 FUSE I/O I/OA Fuse sense and drive
39 PDSG O OA Predischarge PFET control
40 PCHG O OA Precharge PFET control
41 LD I/O I/OA Load detect pin
42 PACK I IA Pack sense input pin
43 DSG O OA NMOS Discharge FET drive output pin
44 NC — — This pin is not connected to silicon.
45 CHG O OA NMOS Charge FET drive output pin
46 CP1 I/O I/OA Charge pump capacitor
47 BAT I P Primary power supply input pin
48 VC16 I IA Sense voltage input pin for the sixteenth cell from the bottom of the stack, balance current input for the sixteenth cell from the bottom of the stack, and top-of-stack measurement point