SLVSNG3 August   2026 DRV8374-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings AUTO
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Timings
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 3x PWM Mode (PWM_MODE = 10b or 11b or MODE_SR Pin is Connected to GVDD with RMODE or to GVDD)
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  GVDD Linear Voltage Regulator
      5. 8.3.5  Charge Pump
      6. 8.3.6  Slew Rate Control
      7. 8.3.7  Cross Conduction (Dead Time)
      8. 8.3.8  Propagation Delay
      9. 8.3.9  Pin Diagrams
        1. 8.3.9.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.9.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.9.3 Open Drain Pin
        4. 8.3.9.4 Push Pull Pin
        5. 8.3.9.5 Four Level Input Pin
      10. 8.3.10 Current Sense Amplifiers
        1. 8.3.10.1 Current Sense Amplifier Operation (23-pin variant)
        2. 8.3.10.2 Current Sense Amplifier Operation (29-pin variant)
      11. 8.3.11 Active Demagnetization
        1. 8.3.11.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 8.3.11.1.1 Automatic Synchronous Rectification in Commutation
          2. 8.3.11.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 8.3.11.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      12. 8.3.12 Cycle-by-Cycle Current Limit
        1. 8.3.12.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      13. 8.3.13 Protections
        1. 8.3.13.1 VM Supply Undervoltage Lockout (RESET)
        2. 8.3.13.2 GVDD Undervoltage Lockout (GVDD_UV)
        3. 8.3.13.3 VCP Charge Pump Undervoltage Lockout (CPUV)
        4. 8.3.13.4 Over Voltage Protections (OV)
        5. 8.3.13.5 Overcurrent Protection (OCP)
          1. 8.3.13.5.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.13.5.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 8.3.13.5.3 OCP Report Only (OCP_MODE = 10b)
          4. 8.3.13.5.4 OCP Disabled (OCP_MODE = 11b)
        6. 8.3.13.6 Thermal Warning (OTW)
        7. 8.3.13.7 Thermal Shutdown (OTS)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 8.4.2 DRVOFF functionality
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI Format
  10. 9 Register Map
    1. 9.1 CONTROL Registers
    2. 9.2 STATUS Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Power Supply Recommendations
      1. 10.2.1 Bulk Capacitance
    3. 10.3 Layout
      1. 10.3.1 Layout Guidelines
      2. 10.3.2 Layout Example
      3. 10.3.3 Thermal Considerations
        1. 10.3.3.1 Power Dissipation
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

5 Device Comparison Table

DEVICE PACKAGES INTERFACE
DRV8374H-Q1 23-pin VQFN (6x4 mm) Hardware, Internal GVDD supply
DRV8374S-Q1 29-pin VQFN (7x5 mm) SPI, Internal GVDD supply
DRV8374H-Q1 Hardware, Internal GVDD supply
Table 5-1 DRV8374S-Q1 (29 pin SPI variant) vs. DRV8374H-Q1 (29 pin Hardware variant) vs.DRV8374GS-Q1 (29 pin SPI variant, Extrenal GVDD) configuration comparison
Parameters DRV8374S-Q1 (SPI variant 29 pin) DRV8374H-Q1 (Hardware variant 29 pin) DRV8374GS-Q1 (SPI variant 29 pin External GVDD)
PWM mode settings PWM_MODE (4 settings) MODE_SR pin (4 settings) PWM_MODE (4 settings)
Slew rate settings SLEW_RATE (4 settings) SLEW pin (4 settings) SLEW_RATE (4 settings)
CSA gain settings CSA_GAIN (4 settings) GAIN pin (4 settings) CSA_GAIN (4 settings)
SDO pin configuration: mode, voltage SDO_ODEN (2 settings), SDO_MD (2 settings) NA SDO_ODEN (2 settings), SDO_MD (2 settings)
Current Limit configuration: Mode, reporting on nFAULT, Blanking time, 100% duty PWM frequency ILIMFLT_MODE (2 settings),ILIM_MODE (2 settings), ILIM_BLANK_SEL (4 settings), PWM_100_FREQ_SEL (4 settings) Current limit reporting on nFAULT is enabled, fixed to coast mode, blanking time set to 5.6µs for slew rate of 50V/µs and 1.8µs for all other slew rates, the 100% duty input PWM cycle is fixed to 20kHz ILIMFLT_MODE (2 settings),ILIM_MODE (2 settings), ILIM_BLANK_SEL (4 settings), PWM_100_FREQ_SEL (4 settings)
Over voltage protection mode OVP_MODE (2 settings), OVP_SEL (2 settings) Over voltage protection is disabled OVP_MODE (2 settings), OVP_SEL (2 settings)
OCP configuration: Mode, level, deglitch OCP_MODE (4 settings), OCP_LVL (2 settings),OCP_DEG (4 settings) and OCP_TRETRY (2 settings) Enabled with automatic retry mode, level is fixed to 50A with 1.2µs deglitch time, 5ms retry time OCP_MODE (4 settings), OCP_LVL (2 settings),OCP_DEG (4 settings) and OCP_TRETRY (2 settings)
Active demagnetization: Enable, comparator threshold, comparator mask time, behaviour during fault EN_ASR (2 settings), EN_AAR (2 settings), AD_COMP_TH_HS & AD_COMP_TH_LS MODE_SR (2 settings), active demag comparator threshold set to 500mA, comparator mask time set to 5.6µs for slew rate of 50V/µs and 1.8µs for all other slew rates. ADMAG_TMARGIN set to 1.6µs, active demag is disabled during OCP. EN_ASR (2 settings), EN_AAR (2 settings), AD_COMP_TH_HS & AD_COMP_TH_LS
Over temperature warning OTW_MODE (2 settings) Reported on nFAULT OTW_MODE (2 settings)