The bulk capacitor must be placed to minimize the distance of the high-current path through the motor driver device. The connecting metal trace widths must be as wide as possible, and numerous vias must be used when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high current. Small-value capacitors such as the charge pump, GVDD, and VREF capacitors must be ceramic and placed closely to device pins. The high-current device outputs must use wide metal traces.

To reduce noise coupling and EMI interference from large transient currents into small-current signal paths, grounding must be partitioned between PGND and AGND. TI recommends connecting all non-power stage circuitry to AGND to reduce parasitic effects and improve power dissipation from the device. Maintain grounds are connected through net-ties or wide resistors to reduce voltage offsets and maintain gate driver performance. TI recommends to have vias on the PGND pads for better thermal efficiency and run a solid PGND plane underneath the device. Multiple vias must be used to connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate the I² × R_DS(on) heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and improve thermal dissipation from the die surface.