For TMUXS130xA to enter
address mode, AC mode must be disabled first by sending 0x0C0002. While in address
mode, the SPI frame expects the following sequence:
- CS is
pulled low
- Default of 24 SCLK cycles (or
32 SCLK cycles if CRC is enabled), 24-bit command (1 R/W bit, 7 address
bits, followed by a 16-bit data)
- CS is
pulled high
When the first bit of command is a 0, this value indicates a write is being
performed. When the first bit is a 1, this value indicates a read is being
performed. The next seven bits following are for the target register address. The
target register is determined during the 8th SCLK cycle. The last 16 bits are
written to the targeted register after CS returns to a HIGH logic level (assuming no
SPI errors), or the bits are ignored when performing a read. While performing a
read, the last 16 bits on SDI are ignored because SDO output the addressed register
state during these last 16 SCLK cycles. During the first eight bits of any command,
SPI sends out eight ERRFLG bits on SDO.