SLVUBT8B November 2020 – June 2022 LP8764-Q1 , TPS6594-Q1
This section lists the different commands and resources available. The description is provided with reference to the PMIC instruction set which is described in the device data sheet.
Not all commands are available on all devices. Refer to the device data sheet.
The BUCK resource is an abstraction of the assembly instructions REG_WRITE_VCTRL_IMM and REG_WRITE_VOUT_IMM. Selecting either the VCTRL or the VOUT tab in the update action window will determine which instruction is applied. Within each tab are the various parameters of each instruction.
BUCKx commands are available for each available BUCK. If BUCKs are multi-phased then the grouping is reflected in the resource name, for example BUCK1_2_3_4, but only the primary BUCK information is shown in the parameter window. In the resulting program, the primary buck will be the only one reflected in the instruction.
The BUCK monitors are a special subset of the REG_WRITE_VCTRL_IMM and REG_WRITE_VOUT_IMM instructions. The parameters which are not used for this resource are not selectable. The VIN tab is the same but represents the monitor voltage setting.
Similar to the BUCKx Monitor, the VMONx is a dedicated voltage monitor found on the LP876x-Q1 family of devices. This resource is only available when the GPIO function is configured to the VMONx function. The VMONx is an abstracted REG_WRITE_MASK_IMM to register address 0×2B (VCCA_VMON_CTRL).
Similar to the BUCK and BUCK Monitor Resources, this is an abstraction of the assembly instructions REG_WRITE_VCTRL_IMM and REG_WRITE_VOUT_IMM. Selecting either the VCTRL or the VOUT tab in the update action window will determine which instruction is applied. Within each tab are the parameters of each instruction.
The nRSTOUT command writes or clears the nRSTOUT bit found in the MISC_CTRL register. The command is an abstraction of the REG_WRITE_MASK_IMM assembly instruction to the address 0x81, register MISC_CTRL. The data and mask are determined by the selection of unchanged, high, or low. The use of the unchanged selection has no impact and only serves as a delay of one instruction cycle.
The nRSTOUT_SOC command writes or clears the nRSTOUT_SOC bit found in the MISC_CTRL register. The command is an abstraction of the REG_WRITE_MASK_IMM assembly instruction to the address 0x81, register MISC_CTRL. The data and mask are determined by the selection of unchanged, high, or low. The use of the unchanged selection has no impact and only serves as a delay of one instruction cycle.
The wait command provides a conditional branch in the instruction set, similar to an if or while statement. When the timeout is provided, the wait condition is effectively an if statement continuing to the next instruction if the condition is true and jumping to the destination if the condition is false. If the timeout is non-zero, then the PMIC will wait until the condition is true and then execute the next instruction or until the timeout is reached and then jump to the destination. The destination must always be after the wait command because the skip count of the wait instruction is always positive. In version 3.0.0, the timeout value must be achievable with the current PFSM_DELAY_STEP. If the timeout is not achievable the GUI will return an error in the PFSM Validation. Use the PFSM_DELAY_STEP command to update the PFSM_DELAY_STEP.
The jump command is special implementation of a wait command which has a timeout of 0 and a condition which is always false. The destination must be after the jump command.
The RESET_BUCKs command is a direct write to the BUCK_RESET_REG register at address 0×87. In this command the resets are per BUCK and each BUCK must be configured even when the BUCKs are multi-phased. The RESET_BUCKs command is translated into a REG_WRITE_MASK_IMM command to address 0×87 to either clear or set bits 0 through 4, representing BUCKS 1-5.
The GO_TO_LP_STANDBY command is a direct write of 1 to the LDOINT disable bit found in the LDOINT_CTRL register, address 0×21. LDOINT is a self-clearing bit. The GO_TO_LP_STANDBY command is a translated into a REG_WRITE_MASK_IMM command to address 0×21, with a data value of 0×01 and a mask of 0xFE.
The SET_WD_LONGWINDOW command is a direct write to the WD_LONGWIN field found in the WD_LONGWIN_CFG register, address 0×405. This field is for programming the duration of the Watchdog Long Window. The SET_WD_LONGWINDOW command is a translated into a REG_WRITE_MASK_IMM command to address 0×405, with a data value range from 0×00 to 0×FF, and a mask of 0×00. A value of 0×00 is approximately 100,ms while a value of 0×FF is approximately 12 minutes.
The GO_TO_LONGWIN command is a direct write of 1 to the WD_RETURN_LONGWIN bit found in the WD_MODE_REG register, address 0×406. This command will cause the watchdog to return to the Long-Window after completion of the current watchdog-sequence. The GO_TO_LONGWIN command is a translated into a REG_WRITE_MASK_IMM command to address 0x406, with a data value of 0×01 and a mask of 0xFE.
The FIRST_STARTUP_DONE command is a direct write of 1 to the FIRST_STARTUP_DONE bit found in the RTC_CTRL_2 register, address 0×C3. The FIRST_STARTUP_DONE command is a translated into a REG_WRITE_MASK_IMM command to address 0×C3, with a data value of 0×80 and a mask of 0×7F.
The INCREASE_RECOVERY_COUNT command is a direct write of 1 to the INCREASE_RECOVERY_COUNT bit found in the RECOV_CNT_PFSM_INCR, address 0×A5. This bit is self-clearing, so each command increments the recovery counter. The INCREASE_RECOVERY_COUNT command is a translated into a REG_WRITE_MASK_IMM instruction to address 0×A5, with a data value of 0×01 and a mask of 0×FE.
The ACTIVATE command is a composite of several commands associated with a power up sequence. These commands include the following:
The DEACTIVATE command is a composite of several commands associated with a power down sequence. This command is not recommended for use in multi-PMIC applications. These commands include the following:
The Deactivate command is not recommended for multi-PMIC applications. The control of parameters SPMI_LPM_EN, VCCA_VMON_EN, AMUXOUT_EN/REFOUT_EN, CLKMON_EN, and LPM_EN are abstracted by the ACTIVATE and DEACTIVATE commands. SPMI_LPM_EN sets SPMI in a low power mode which stops SPMI WD (Bus heartbeat). In multi-PMIC applications, the SPMI_LPM_EN must be handled at similar times to prevent SPMI WD failures. Therefore, to mitigate clock variations, setting and clearing of SPMI_LPM_EN must be done early in the sequence of each PMIC.
The LPM_EN parameter puts the PMIC in a low power mode. The intended use case is for the PFSM to set LPM_EN upon entering a low power consumption state. The end objective is to disable the digital oscillator to reduce power consumption. Refer to the data sheet for functions disabled when LPM_EN is set.
| TO_SAFE | TO_STANDBY | TO_RETENTION | TO_ACTIVE |
|---|---|---|---|
| SPMI_LPM_EN=1, FORCE_EN_DRV_LOW =1 | SPMI_LPM_EN=1, FORCE_EN_DRV_LOW =1 | nRSTOUT = 0, nRSTOUT_SOC=0 | LPM_EN=0, AMUXOUT_EN = 1, CLKMON_EN = 1 |
| nRSTOUT = 0, nRSTOUT_SOC=0 | nRSTOUT = 0, nRSTOUT_SOC=0 | SPMI_LPM_EN=1, FORCE_EN_DRV_LOW =1 | SPMI_LPM_EN = 0 |
| ... | ... | ... | ... |
| LPM_EN=1, AMUXOUT_EN = 0, CLKMON_EN = 0 | LPM_EN=1, AMUXOUT_EN = 0, CLKMON_EN = 0 | LPM_EN=1, AMUXOUT_EN = 0, CLKMON_EN = 0 | FORCE_EN_DRV_LOW =0 |
| nRSTOUT = 1, nRSTOUT_SOC=1 |
The key requirement for multi-pmic solutions is that the SPMI_LPM_EN should occur first while the LPM_EN should occur last in the sequence. Because the DEACTIVATE command encapsulates both the LPM_EN and the SPMI_LPM_EN in a set of executions placing the DEACTIVATE at the beginning or the end will violate one of the requirements.
The ENDRV command is a direct write to the FORCE_EN_DRV_LOW bit found in the ENABLE_DRV_STAT register, address 0×82. The ENDRV command is a translated into a REG_WRITE_MASK_IMM command to address 0×82, with a data value of 0×08 or 0×00, and a mask of 0×F7.
The DELAY_IMM command is a direct representation of the DELAY_IMM instruction. The delay specified in this command is applied to all devices. In version 3.0.0, the GUI will no longer automatically adjust the PFSM_STEP_SIZE if the size of the DELAY_IMM cannot be achieved with the existing PFSM_STEP_SIZE. The user is responsible for managing the PFSM_STEP_SIZE for the desired delays. This also applies to all instructions which have a timing component. In the event that the delay cannot be achieved an error is provided in the PFSM Validation.
The REG_WRITE_MASK_IMM command is a direct representation of the REG_WRITE_MASK_IMM instruction. The REG_WRITE_MASK_IMM command includes a mask to write or clear specific bits without impacting other bits within the register.
The TRIG_MASK command is a direct representation of the TRIG_MASK instruction. The trigger mask will determine which interrupts are enabled and disabled. Using the Automatic trigger will set the trigger based upon the trigger settings from the TARGET STATE.
The REG_WRITE_IMM command is a direct representation of the REG_WRITE_IMM instruction. The REG_WRITE_IMM command overwrites all bits within the register specified.
The REG_WRITE_MASK_SREG command is a direct representation of the REG_WRITE_ MASK_SREG instruction. The REG_WRITE_ MASK_SREG command includes a mask to write or clear specific bits without impacting other bits within the register. The data is sourced from the specified scratch register.
The SREG_READ_REG command is a direct representation of the SREG_READ_REG instruction. This command copies the contents of the register to the specified scratch register.
The SREG_WRITE_IMM command is a direct representation of the SREG_WRITE_IMM instruction.
The DELAY_SREG command is a direct representation of the DELAY_SREG instruction. This delay is different than the other delays found in the resources and commands. The delay is only applied to the device specified.
The PFSM_DELAY_STEP is a direct representation of the SET_DELAY instruction which writes to the PFSM_DELAY_STEP register.
The END command is direct representation of the END instruction. This can be used to terminate branches created in the PFSM sequence using the JUMP and WAIT commands.