SLVUC99A January   2022  – January 2022 DRA829V , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  9. 8References
  10. 9Revision History

3.2 Control Mapping

Figure 3-2 shows the digital control signal mapping between processor and PMIC devices. For the two PMIC devices to work together, the primary PMIC and secondary PMIC must establish an SPMI communication channel. This allows the two TPS6594-Q1 to synchronize their internal Pre-Configurable State Machines (PFSM) so that they operate as one PFSM across all power and digital resources. The GPIO_5 and GPIO_6 pins on the TPS6594-Q1 are assigned for this functionality. In addition, the LDOVINT pin of the primary PMIC is connected to the ENABLE pin of the secondary PMIC in order to correctly initiate the PFSM.

Other digital connections from the TPS6594-Q1 PMICs to the processor provide error monitoring, processor reset, processor wake up, and system low-power modes. Specific GPIO pins have been assigned to key signals in order to ensure proper operation during low power modes when only a few GPIO pins remain operational.

The digital connections shown in Figure 3-2 allow system features including 'MCU-only, MCU Safety Island' and DDR Retention modes, functional safety up to ASIL-D, and compliant dual voltage SD card operation.

Figure 3-2 TPS6594-Q1 Digital Connections
  1. PMIC IO can have distinct power domains for input and output functionality. The SDA function for I2C1 and I2C2 use the VINT voltage domain as an input and the VIO voltage domain as an output. Please refer to the device datasheet for a complete description. The PMIC voltage domains indicated are for the PDN-0C NVM configuration.
  2. PMIC_Wake1 is typically a CAN PHY INH output.
  3. WKUP2 triggers a transition to MCU Only state. LP_WKUP1 and WKUP1 transition to the ACTIVE state. Figure 6-1
Note: The PMIC voltage domain of an IO can be different depending upon configuration. When configured as an input GPIO3 and GPIO4 are in the VRTC domain. When configured as an output, GPIO3 and GPIO4 are in the VINT domain.
Note: In addition to the I2C signals, four additional signals are open-drain outputs and require a pullup to a specific power rail. Please refer to Table 3-2 for a list of the signals and the specific power rail.
Table 3-2 Open-drain signals and Power Rail
PDN SignalPullup Power Rail
H_MCU_INTnVDD_MCUIO_3V3
H_MCU_PORz_1V8VDA_MCU_1V8
H_SOC_PORz_1V8VDA_MCU_1V8
H_DDR_RET_1V1VDD_DDR_1V1_REG
H_WKUP_I2C0VDD_MCUIO_3V3
H_MCU_I2C0_SCL/SDAVDD_MCUIO_3V3

Please use Table 3-3 as a guide to understand GPIO assignments required for each PDN system feature. If the feature listed is not required, the digital connection can be removed; however, the GPIO pin is still configured per NVM defined default function shown. After the processor has booted up, the processor can reconfigure unused GPIOs to support new functions. This is possible as long as that function is only needed after boot and default function does not cause any conflicts with normal operations (for example, two outputs driving same net). For details on how functional safety related connections help achieve functional safety system-level goals, see Section 4.

Table 3-3 Digital Connections by System Feature
DeviceGPIO MappingSystem Features(1)
PMIC PinNVM FunctionPDN SignalsActive SoCFunctional SafetyMCU - only MCU-Safety IslandDDR RetentionSD Card
TPS65941213-Q1nPWRON/ ENABLEEnableSOC_PWR_ONR
INTINTH_MCU_INTnR
nRSTOUTnRSTOUTH_MCU_PORz_1V8RR
SCL_I2C1SCL_I2C1H_WKUP_I2C0R
SDA_I2C1SDA_I2C1H_WKUP_I2C0R
GPIO_1SCL_I2C2H_MCU_I2C0_SCLR
GPIO_2SDA_I2C2H_MCU_I2C0_SDAR
GPIO_3nERR_SoCH_SOC_SAFETY_ERRnR
GPIO_4LP_WKUP1(2)PMIC_WAKE1R
GPIO_5SCLK_SPMILEOA_SCLKR
GPIO_6SDATA_SPMILEOA_SDATAR
GPIO_7nERR_MCUH_MCU_SAFETY_ERRnR
GPIO_8DISABLE_WDOGPMICA_GPIO8(4)(4)
GPIO_9GPOEN_MCU3V3IO_LDSWRR
GPIO_10WKUP1PMICA_GPIO10/ H_PMIC_PWR_EN1R
GPIO_11nRSTOUT_SOCH_SOC_PORz_1V8R
TPS65941111-Q1nPWRON/ENABLEENABLEVINT_LEOA_1V8R
nINTnINTH_MCU_INTn
nRSTOUTnRSTOUTUnused
SCL_I2C1SCL_I2C1H_WKUP_I2C0R
SDA_I2C1SCL_I2C1H_WKUP_I2C0R
GPIO_1GPIUnused(5)
GPIO_2GPISEL_SDIO_3V3_1V8n(3)R
GPIO_3GPOEN_DDR_BUCKROR
GPIO_4(6)GPOH_DDR_RET_1V1R
GPIO_5SCLK_SPMILEOA_SCLKR
GPIO_6SDATA_SPMILEOA_SDATAR
GPIO_7GPIUnused(5)
GPIO_8GPIUnused(5)
GPIO_9GPOEN_EFUSE_LDO(5)
GPIO_10WKUP2Unused(5)
GPIO_11GPOEN_3V3IO_LDSWR
(1) R is Required. O is optional.
(2) LP_WKUP1 function is masked in the static settings. Instructions for unmasking the function are provided in Section 7.1.3, Section 7.2 and Section 7.3.
(3) This pin is an input with an internal pulldown enabled. A rising edge on this GPI initiates the FSM trigger and associated sequence. The sequence configures LDO1 to bypass mode, supplying 3.3 V. A falling edge triggers an alternate sequence which configures LDO1 to LDO mode, supplying 1.8 V. See also Table 6-1
(4) If it is desired to disable the watchdog through hardware, GPIO_8 is required and must be set high by the time nRSTOUT goes high. After nRSTOUT is high, the watchdog state is latched and the pin can be configured for other functions through software.
(5) This GPIO is not required for power sequencing or PMIC functionality and can be configured by software for a different purpose if desired.
(6) GPIO4 of the TPS65941111 is not part of the power sequences, Section 6.3. This GPIO must be configured by the SOC at runtime.