SLVUC99A January   2022  – January 2022 DRA829V , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  9. 8References
  10. 9Revision History

3.1 Power Mapping

Figure 3-1 shows the power mapping between the dual TPS6594-Q1 PMIC power resources and processor voltage domains required to support independent MCU and Main power rails. In this configuration, both PMICs use a 3.3 V input voltage. For Functional Safety applications, there is a protection FET before VCCA that connects to the OVPGDRV pin of the primary PMIC, allowing voltage monitoring of the input supply to the PMICs.

For SD card dual-voltage I/O support (3.3 V and 1.8 V), LDO1 of the TPS65941111-Q1 device can be used. A processor GPIO control signal with a logic high default value is used to set SD VIO to 3.3 V initially. During processor power up, the boot loader SW can set GPIO signal low to select 1.8 V level as needed for high-speed card operation per SD specification. This allows control of the LDO1 voltage without the need for the MCU processor to establish I2C communication with the PMICs during boot from SD card operations.

This PDN uses four discrete power components with three being required and one is optional depending upon end product features. The two TPS22965-Q1 Load Switches connect VCCA_3V3 power rail to supply OV protected 3.3 V to processor I/O domains. Two load switches are required in order to enable isolation between MCU and Main processor sub-sections for MCU Safety Island or MCU Only low power operations. The unused feedback pin, FB_B3, of the TPS65941213 has been configured per NVM settings, Table 5-3, to provide voltage monitoring for VDD_MCUIO_3V3_LS power rail. This enables all of the MCU processor power supply inputs to have voltage monitoring coverage as needed for functional safety ASIL-B and higher systems. The third discrete device is a TPS62813-Q1 Buck Converter which supplies the LPDDR4 SDRAM component with required 1.1V supply. The last discrete power component is an optional TLV73318-Q1 LDO that can be used if an end product uses a high security processor type and desires the capability to program Efuse values on-board. If this feature is not desired, then this LDO can be omitted and processor pins terminated per data manual recommendations.

Note: The PMIC voltage monitor on FB_B3 must be connected to 3.3 V. The VMON_ABIST_EN=1 for both the primary and secondary PMICs. If 3.3 V is not connected to FB_B3 when the monitor is enabled then the self-test fails, the BIST_FAIL_INT interrupt is set, and the device goes to the hardware SAFE RECOVERY state, see Figure 6-1, and main processor voltages are disabled.
Figure 3-1 Power Connections

  • * VDD_CPU_AVS, boot voltage of 0.8 V then software sets device specific AVS; 0.68 V – 0.72 V.
  • ** VDD_SD_DV, 3.3 V then software changes to 1.8 V per HS-SD.

Table 3-1 identifies which power resources are required to support different system features. In the Active SoC column, there is an additional option for including or excluding the VPP_x(EFUSE) rail. LDO1 and LDO2 of TPS65941111, which support optional SD CARD and USB Interface features, are enabled as part of the power on sequence as shown in Figure 6-11. Even if these System Features are not used, the regulators are energized as part of the power up sequence.

Table 3-1 PDN Power Mapping and System Features
Power MappingSystem Features(1)
DevicePower ResourcePower RailsProcessor and Memory DomainsActive SoCMCU - onlyDDR RetentionSD CardUSB Interface
TPS65941213-Q1BUCK123VDD_CPU_AVSVDD_CPUR
FB_B3VDDSHVx_MCU (3.3 V)RR
BUCK4VDD_MCU_0V85VDDAR_MCU, VDD_MCURR
BUCK5VDD_PHY_1V8VDDA_1P8_PHYsR
LDO1VDD1_DDR_1V8Mem: VDD1RO(2)R(2)
LDO2VDD_MCUIO_1V8VDDSHVx_MCU (1.8 V)RR
Mem: VCC
LDO3VDA_DLL_0V8VDDA_0P8_PLLs/DLLsR
LDO4VDA_MCU_1V8VDDA_xRR
TPS65941111-Q1BUCK1234VDD_CORE_0V8VDD_CORE, VDDA_0P8_PHYsR
BUCK5VDD_RAM_0V85VDDAR_CPU/CORER
LDO1VDD_SD_DVVDDSHV5R
LDO2VDD_USB_3V3VDDA_3P3_USBR
LDO3VDD_IO_1V8VDDS_MMC0R
Mem: VCCQ
LDO4VDA_PLL_1V8VDDA_1P8_PLLsR
TPS22965-Q1Load SwitchVDD_MCUIO_3V3VDDSHVx_MCU (3.3 V)RR
TPS22965-Q1Load SwitchVDD_IO_3V3VDDSHV0-4,VDDSHV6 (3.3 V)R
TLV73318P-Q1LDOVPP_EFUSE_1V8VPP_x(EFUSE)O
TPS62813-Q1BUCKVDD_DDR_1V1VDDS_DDR_BIAS, VDDS_DDR_IORO(3)R(3)
Mem: VDD2
(1) 'R' is required and 'O' is optional.
(2) LDO1 of the TPS65941213-Q1 remains on when TRIGGER_I2C_7, in FSM_I2C_TRIGGERS Register, is set.
(3) The TPS62813-Q1 is controlled by the TPS65941111-Q1 GPIO3 and remains active while TRIGGER_I2C_7, in FSM_I2C_TRIGGERS, is set.