SLVUC99A January   2022  – January 2022 DRA829V , TDA4VM , TPS6594-Q1

 

  1.   Trademarks
  2. 1Introduction
  3. 2Device Versions
  4. 3Processor Connections
    1. 3.1 Power Mapping
    2. 3.2 Control Mapping
  5. 4Supporting Functional Safety Systems
    1. 4.1 Achieving ASIL-B System Requirements
    2. 4.2 Achieving up to ASIL-D System Requirements
  6. 5Static NVM Settings
    1. 5.1  Application-Based Configuration Settings
    2. 5.2  Device Identification Settings
    3. 5.3  BUCK Settings
    4. 5.4  LDO Settings
    5. 5.5  VCCA Settings
    6. 5.6  GPIO Settings
    7. 5.7  Finite State Machine (FSM) Settings
    8. 5.8  Interrupt Settings
    9. 5.9  POWERGOOD Settings
    10. 5.10 Miscellaneous Settings
    11. 5.11 Interface Settings
    12. 5.12 Multi-Device Settings
    13. 5.13 Watchdog Settings
  7. 6Pre-Configurable Finite State Machine (PFSM) Settings
    1. 6.1 Configured States
    2. 6.2 PFSM Triggers
    3. 6.3 Power Sequences
      1. 6.3.1 TO_SAFE_SEVERE and TO_SAFE
      2. 6.3.2 TO_SAFE_ORDERLY and TO_STANDBY
      3. 6.3.3 ACTIVE_TO_WARM
      4. 6.3.4 ESM_SOC_ERROR
      5. 6.3.5 PWR_SOC_ERROR
      6. 6.3.6 MCU_TO_WARM
      7. 6.3.7 TO_MCU
      8. 6.3.8 TO_ACTIVE
      9. 6.3.9 TO_RETENTION
  8. 7Application Examples
    1. 7.1 Moving Between States; ACTIVE, MCU ONLY, and RETENTION
      1. 7.1.1 ACTIVE
      2. 7.1.2 MCU ONLY
      3. 7.1.3 RETENTION
    2. 7.2 Entering and Exiting Standby
    3. 7.3 Entering and Existing LP_STANDBY
    4. 7.4 Runtime Customization
  9. 8References
  10. 9Revision History

7.4 Runtime Customization

The TPS65941213 GPIO8 is configured as an input to disable the watchdog. Typically, during development this pin is tied high, so that when the nRSTOUT bit is set WD_PWRHOLD is also set. The configuration of this pin can be utilized for other features or functions but this requires servicing the watchdog before it expires. The watchdog long window is 772 seconds, Table 5-13. 


Write 0x12:0x09:0x00:0xBF  // Disable Watchdog
Write 0x48:0x38:0x01:0x00  // configure GPIO8 as a pushpull output

When it is time to enable and configure the watchdog, then in addition to enabling the watchdog the WD_PWR_HOLD must be cleared.


Write 0x12:0x09:0x00:0xFB  // Clear WD_PWRHOLD
Write 0x12:0x09:0x40:0xBF  // Enable Watchdog

In addition to the GPIO8 of the TPS65941213 there are also the feedback pins for BUCK3 and BUCK4 on the TPS65941111. These monitors can be used independently since the BUCK3 and BUCK4 regulators are multiphased with BUCKs 1 and 2. When enabling a monitor, the built in self-test is performed. Please refer to the datasheet for an explanation of the monitor self-test. If the self-test fails this results in a Moderate error which triggers the TO_SAFE_ORDERLY power sequence.

Unlike the GPIO, the BUCK monitor can become part of the PFSM by assigning a group to the BUCK regulator and unmasking the OV/UV interrupts. Per the Table 5-7 the BUCK3_GRP_SEL and BUCK4_GRP_SEL are not assigned a group.

Table 7-3 Rail Group Associations
Selected Rail group Selection PFSM Trigger Description
No Group Assigned None OV/UV can set nINT pin for MCU interrogation.
MCU Rail Group MCU Power Error OV/UV can trigger TO_SAFE
Soc Rail Group SoC Power Error OV/UV can trigger PWR_SOC_ERROR
Other Rail Group Orderly Shutdown OV/UV can triggerTO_SAFE_ORDERLY

In this example BUCK3 is used to monitor a 1.1V supply and BUCK4 is used to monitor a 0.8V supply. The wait statement ensures that the built in self-test of the monitors is completed before the OV and UV monitors are unmasked. Refer to the TPS6594-Q1Power Management IC (PMIC) with 5 Bucks and 4 LDOs for Safety-Relevant Automotive Applications datasheet for more details.


Write 0x4C:0x12:0x73:0x00  // Set to 1.1V
Write 0x4C:0x14:0x37:0x00  // Set to 0.8V
Write 0x4C:0x09:0x07:0xF1  // Set slew rate to 0.31mV/us
Write 0x4C:0x0B:0x07:0xF1
Write 0x4C:0x41:0xA0:0x0F  // SOC rail group
Write 0x4C:0x4A:0x33:0xCC  // Mask OV/UV
Write 0x4C:0x08:0x10:0xEF  // Enable BUCK3 Monitor
Write 0x4C:0x0A:0x10:0xEF  // Enable BUCK4 Monitor
// Startup = 220us, ramp = 42us, settling = 105us, OV/UV test=50us
wait 500us
Write 0x4C:0x4A:0x00:0xCC  // Unmask OV/UV

With the TO_SAFE and TO_SAFE_ORDERLY sequences the PMICs transition through the SAFE RECOVERY state as well as hardware states INIT and BOOT BIST. Through this transition the user registers are restored with the NVM settings. For both the GPIO and BUCK monitor customizations, these customizations are not preserved and must be re-applied with every power cycle and transition through the hardware states.