SLVUDB0A August 2025 – October 2025
The ADS9324 uses SPI to configure the internal device registers using pins SCLK, SDI, SDOUT, and CSn. The data interface can be configured to be output in 1, 2, 4, or 8 lanes. The EVM and GUI software allows evaluation of the 8-lane data interface mode. These SPI signals, CONVST, DRDY, and D0-D7 signals are available using test points on J20 and J21 for scope measurements as indicated in PCB silkscreen.
The FMC connector pinout below can also be interfaced with standard FPGA development kits. Note that the TI-provided software GUI is only compatible with the TSWDC155EVM and third-party software development is not supported.
Figure 2-5 shows the necessary decoupling capacitors for analog supplies, digital supplies, and ADC reference voltages.