SLVUDB0A August   2025  – October 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 ADS9324EVM Quick Start Guide
    2. 2.2 Analog Interface
      1. 2.2.1 ADC Input SMA Connections
      2. 2.2.2 Voltage Reference
    3. 2.3 Digital Interface and Clock Inputs
      1. 2.3.1 Digital Interface Connections
      2. 2.3.2 Level Translators
    4. 2.4 Power Supplies
      1. 2.4.1 USB Power and When to Power the Board Externally
  7. 3Software
    1. 3.1 ADS9324EVM Software Installation
      1. 3.1.1 USB Driver Installation
    2. 3.2 ADS9324EVM Software
      1. 3.2.1 Using Configuration Tab
      2. 3.2.2 Using the Data Capture Tab
      3. 3.2.3 Using the Linearity Analysis Tab
      4. 3.2.4 Using the Histogram Analysis Tab
  8. 4Hardware Design Files
    1. 4.1 Schematics
      1. 4.1.1 ADS9324EVM Schematics
    2. 4.2 Layout
    3. 4.3 Bill of Materials (BOM)
      1. 4.3.1 ADS9324EVM Bill of Materials (BOM)
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Related Documentation
  11. 7Revision History

2.3.2 Level Translators

The ADS9324EVM has level translators to shift 3.3V digital signals to 1.8V for use with the FPGA on the TSWDC155EVM. This is done for testing purposes. By default, the EVM IOVDD is set to 1.8V, so the level shifters are not necessary. The IOVDD voltage can be changed to 3.3V to interface with an MCU. Instructions on how to configure the IOVDD voltage on the EVM can be found in Power Supplies.

ADS9324EVM Level TranslatorsFigure 2-6 Level Translators