SLVUDB0A August   2025  – October 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  6. 2Hardware
    1. 2.1 ADS9324EVM Quick Start Guide
    2. 2.2 Analog Interface
      1. 2.2.1 ADC Input SMA Connections
      2. 2.2.2 Voltage Reference
    3. 2.3 Digital Interface and Clock Inputs
      1. 2.3.1 Digital Interface Connections
      2. 2.3.2 Level Translators
    4. 2.4 Power Supplies
      1. 2.4.1 USB Power and When to Power the Board Externally
  7. 3Software
    1. 3.1 ADS9324EVM Software Installation
      1. 3.1.1 USB Driver Installation
    2. 3.2 ADS9324EVM Software
      1. 3.2.1 Using Configuration Tab
      2. 3.2.2 Using the Data Capture Tab
      3. 3.2.3 Using the Linearity Analysis Tab
      4. 3.2.4 Using the Histogram Analysis Tab
  8. 4Hardware Design Files
    1. 4.1 Schematics
      1. 4.1.1 ADS9324EVM Schematics
    2. 4.2 Layout
    3. 4.3 Bill of Materials (BOM)
      1. 4.3.1 ADS9324EVM Bill of Materials (BOM)
  9. 5Additional Information
    1. 5.1 Trademarks
  10. 6Related Documentation
  11. 7Revision History

2.4 Power Supplies

By default, the TSWDC155EVM provides the ADS9324EVM with a 3.3V supply (3P3V). The ADS9324EVM has a TPS61070 boost converter that boosts the 3.3V supply to 5.4V. By default, this voltage is applied to low-dropout regulators (LDOs) to derive the AVDD_5V, AVDD_1V8, and IOVDD supplies when JP1 is in the [1-2] position. U5 (TPS7A2050) provides the 5V AVDD_5V supply, U6 (TPS7A2018) provides the AVDD_1V8 supply, and U4 (TPS7A2033) provides 3.3V for IOVDD, respectively. The LDO input voltage can be changed to an external source (5.2V to 5.5V) applied to terminal block J19 by placing a shunt on JP1 in the [2-3] position. In this case, U3 (LM66100) provides reverse polarity protection if the connection is wired incorrectly.

IOVDD can be either 1.8V or 3.3V. This allows ADS9324 the interface with both FPGAs and MCUs.

To set the IOVDD = 1.8V on the EVM:

  • Populate R75 and depopulate R76

To set the IOVDD = 3.3V on the EVM:

  • Populate U4 with TPS7A2033
  • Populate R76 and depopulate R75

Figure 2-7 shows the power tree schematic for the ADS9324EVM.

ADS9324EVM Power Entry and RegulatorsFigure 2-7 Power Entry and Regulators