SLVUDF7 October   2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Electrostatic Discharge Caution
    3. 1.3 Kit Contents
    4. 1.4 Specification
    5. 1.5 Device Information
    6. 1.6 Hot Surface Warning
  8. 2Hardware
    1. 2.1 Setup and Connections
    2. 2.2 Jumper Settings
    3. 2.3 Power-Supply Connections
    4. 2.4 Analog Input and Output Connections
    5. 2.5 Reference Input
    6. 2.6 Digital Input Pins and Gain Control
    7. 2.7 Modifications
  9. 3Hardware Design Files
    1. 3.1 PCB Layout
    2. 3.2 Schematic
    3. 3.3 Bill of Materials
  10. 4Additional Information
    1. 4.1 Trademarks
  11. 5Related Documentation

2 Hardware

This EVM provides access to the features and measures the performance of the PGA848 device. By default, the PGA848EVM programmable gain instrumentation amplifier is configured to a gain of 0.5V/V. The evaluation board provides jumpers J10 (A2), J11 (A1), and J12 (A0) to set the PGA848 gain.

The device uses two sets of voltage supplies: input stage and output stage. The output-stage power supplies are decoupled from the input stage to limit the PGA848 output-swing voltage level protecting the ADC or downstream device against overdrive damage. The input-stage supplies, VS+ and VS–, are accessible using connector J13. The output-stage supplies, LVDD+ and LVSS–, are accessible using connector J14. Selectable jumpers J9 and J16 set the output-stage supply voltage level equal to the input-stage supplies (default), or to external voltages using connector J14.

The PGA848 incorporates features that simplify interfacing to a single-ended or pseudo-differential input ADC. The REF pin sets the reference point for the output voltage of the PGA848. The REF pin must be driven with a low-impedance source, and the evaluation board provides an optional buffer (U2) to drive the REF pin. Selectable jumper J1 provides options to set the REF pin voltage externally through connector J2, or connects the REF to GND, or sets the REF to the PGA848 output-stage supplies (LVDD+ and LVSS–) mid-voltage value. The PGA848EVM allows access to the DA_IN– and DA_IN+ pins with optional capacitors C4 and C14. These capacitors are in parallel with the PGA848 output-stage difference amplifier internal resistors to implement noise filtering. Figure 2-1 displays a simplified block diagram of the PGA848EVM. For a full schematic of the PGA848EVM, see Figure 3-6.

PGA848EVM PGA848EVM Simplified SchematicFigure 2-1 PGA848EVM Simplified Schematic