SLVUDI4 October   2025

 

  1.   1
  2.   Description
  3.   Features
  4. 1Applications
  5.   5
  6. 2Evaluation Module Overview
    1. 2.1 Introduction
    2. 2.2 Kit Contents
    3. 2.3 Specification
    4. 2.4 Device Information
  7. 3Hardware
    1. 3.1 Input and Output Connections
  8. 4Implementation Results
    1. 4.1 Test Setup
      1. 4.1.1 Start-Up Procedure
    2. 4.2 Output Current Setting
  9. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 Layout
    3. 5.3 Bill of Materials
  10. 6Additional Information
    1. 6.1 Trademarks
  11. 7References

5.2 Layout

Figure 5-2 to Figure 5-4 show the board layout for the TPS923610EVM. The top layer contains the main power traces for PVIN, VOUT, and ground. Connections for the pins of the TPS923610 and a large area filled with ground are also on the top layer. Most of the signal traces are also located on the top side. The decoupling capacitors C4, and C5 are located as close to the IC as possible. Both the top layer and bottom layer use 2oz copper thickness.

TPS923610EVM TPS923610EVM Top AssemblyFigure 5-2 TPS923610EVM Top Assembly
TPS923610EVM TPS923610EVM Top LayerFigure 5-3 TPS923610EVM Top Layer
TPS923610EVM TPS923610EVM Middle Layer 1Figure 5-4 TPS923610EVM Middle Layer 1
TPS923610EVM TPS923610EVM Middle Layer 2 Figure 5-5 TPS923610EVM Middle Layer 2
TPS923610EVM TPS923610EVM Bottom Layer Figure 5-6 TPS923610EVM Bottom Layer