SLVUDU7 April   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
      1. 1.4.1 Application Circuit Diagram
  8. 2Hardware
    1. 2.1 Test Setup and Procedure
      1. 2.1.1 EVM Connections
      2. 2.1.2 Test Equipment
      3. 2.1.3 Recommended Test Setup
        1. 2.1.3.1 Input Connections
        2. 2.1.3.2 Output Connections
      4. 2.1.4 Test Procedure
        1. 2.1.4.1 Line and Load Regulation, Efficiency
  9. 3Implementation Results
    1. 3.1 Test Data and Performance Curves
      1. 3.1.1 Efficiency
      2. 3.1.2 Thermal Performance
      3. 3.1.3 Operating Waveforms
        1. 3.1.3.1 Load Transient Response
        2. 3.1.3.2 Start-Up With VIN
        3. 3.1.3.3 Start-Up and Shutdown With ENABLE On and Off
        4. 3.1.3.4 Switching Operation
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
      1. 4.2.1 Component Drawings
      2. 4.2.2 Layout Guidelines
        1. 4.2.2.1 Power Stage Layout
        2. 4.2.2.2 Small-signal Component Layout
        3. 4.2.2.3 Thermal Design and Layout
        4. 4.2.2.4 Ground Plane Design
    3. 4.3 Bill of Materials
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
        1. 7.2.1.1 Low-EMI Design Resources
        2. 7.2.1.2 Thermal Design Resources
        3. 7.2.1.3 PCB Layout Resources

1.4.1 Application Circuit Diagram

Figure 1-1 shows an LMG708B0 GaN two-phase synchronous buck regulator with adjustable output voltage set by feedback resistors designated as RFB1 and RFB2. Alternatively, tying the FB pin of the primary IC high or low establishes fixed output settings of 12V and 5V, respectively.

LMG708B0-EVM2PH LMG708B0 Two-Phase GaN Synchronous Buck Regulator Simplified Schematic Figure 1-1 LMG708B0 Two-Phase GaN Synchronous Buck Regulator Simplified Schematic

Setting the CNFG resistor to 23.7kΩ on the primary IC and 0Ω (or 100kΩ) on the secondary IC establishes a two-phase configuration with 180° clock synchronization. Connect SYNCOUT of the primary IC to FPWM/SYNC of the secondary. Also, tie the respective COMP, IMON, VSET, and ISET pins between each converter and revise the compensation components as needed. Defined by components RCOMP, CCOMP and CHF, a type-II compensation network facilitates setting the CV-loop crossover frequency and phase margin to meet a target load transient response specification. Tie the IMON pins to GND if CC-loop operation is not required, in which case VSET and ISET of each IC can be left open circuit. Set FPWM or PFM operating modes by tying FPWM/SYNC of the primary IC and FB of the secondary IC high or low, respectively.

The BIAS input derives current from the output (at voltages above the 4.6V switchover threshold) to achieve lower IC power loss and improved efficiency at light loads in particular. Resistor RIMON sets the CC-loop setpoint and capacitor CIMON provides CC-loop stability. Tie IMON to GND if CC-loop operation is not required, in which case VSET and ISET of each IC can be left open circuit. Finally, resistors RUV1 and RUV2 set the input UVLO turn-on and turn-off voltage thresholds. Not shown in Figure 1-1 is an EMI filter stage at the input.