SLVUDU7 April   2026

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specifications
    4. 1.4 Device Information
      1. 1.4.1 Application Circuit Diagram
  8. 2Hardware
    1. 2.1 Test Setup and Procedure
      1. 2.1.1 EVM Connections
      2. 2.1.2 Test Equipment
      3. 2.1.3 Recommended Test Setup
        1. 2.1.3.1 Input Connections
        2. 2.1.3.2 Output Connections
      4. 2.1.4 Test Procedure
        1. 2.1.4.1 Line and Load Regulation, Efficiency
  9. 3Implementation Results
    1. 3.1 Test Data and Performance Curves
      1. 3.1.1 Efficiency
      2. 3.1.2 Thermal Performance
      3. 3.1.3 Operating Waveforms
        1. 3.1.3.1 Load Transient Response
        2. 3.1.3.2 Start-Up With VIN
        3. 3.1.3.3 Start-Up and Shutdown With ENABLE On and Off
        4. 3.1.3.4 Switching Operation
  10. 4Hardware Design Files
    1. 4.1 Schematic
    2. 4.2 PCB Layout
      1. 4.2.1 Component Drawings
      2. 4.2.2 Layout Guidelines
        1. 4.2.2.1 Power Stage Layout
        2. 4.2.2.2 Small-signal Component Layout
        3. 4.2.2.3 Thermal Design and Layout
        4. 4.2.2.4 Ground Plane Design
    3. 4.3 Bill of Materials
  11. 5Compliance Information
    1. 5.1 Compliance and Certifications
  12. 6Additional Information
    1. 6.1 Trademarks
  13. 7Device and Documentation Support
    1. 7.1 Device Support
      1. 7.1.1 Development Support
    2. 7.2 Documentation Support
      1. 7.2.1 Related Documentation
        1. 7.2.1.1 Low-EMI Design Resources
        2. 7.2.1.2 Thermal Design Resources
        3. 7.2.1.3 PCB Layout Resources

4.2.2.2 Small-signal Component Layout

The following considers components related to the analog and feedback signals as well as current sensing:

  • Place small-signal components close to the power IC. Insert at least one inner plane, connected to ground, for noise shielding. Isolate the small-signal traces from noisy power traces and polygons.
  • Use a dedicated AGND island connected to the AGND pin of the IC. PGND and AGND connect internally in the IC, obviating the need for a connection on the PCB.
  • Place all sensitive analog traces and components related to COMP, FB, CSA, CSB/VOUT, VSET, ISET, IMON, and RT away from the high-voltage switching node to avoid mutual coupling. Pay particular attention to shielding the feedback (FB) and current sense (CSA and CSB/VOUT) traces from power traces and components.
  • Locate the upper and lower feedback resistors (if required) close to the FB pin, keeping the FB trace as short as possible. Route the trace from the upper feedback resistor to the required output voltage sense point at the load.
  • Route the CSA and CSB/VOUT sense traces as a differential pair to minimize noise pickup and use Kelvin connections to the applicable shunt resistor.