SNAA435 Application note

FPD-Link III devices require different REFCLK frequencies based on the imager or camera pixel clock (PCLK) frequency used in the system. Similarly, the time-domain jitter specification depends on the PCLK frequency, UI, and various link configuration settings. The summary below lists the time-domain and frequency-domain jitter limits and UI definitions for all FPD-Link III devices which require an external REFCLK. All devices can support a standard 1.8V LVCMOS clock input with ±50ppm frequency accuracy. For time-domain jitter measurements, a custom second order PLL model needs to be configured in the jitter analysis software tool. The following loop bandwidth, low pass filter, and BER settings are used for time-domain jitter analysis for all FPD-Link III devices:

Equation 1.

L P F = \frac{f_{O S C}}{20}

Equation 2.

C D R P L L L B W = \frac{f_{O S C}}{15}

Equation 3.

B E R = 10^{- 10}

DS90UB933-Q1 and DS90UB633A-Q1 UI Definition and Time-Domain Jitter Limit

Equation 4.

10 - b i t M o d e : U I = \frac{1}{\frac{f_{P C L K}}{2} \times 28}

Equation 5.

12 - b i t M o d e : U I = \frac{1}{f_{P C L K} \times \frac{2}{3} \times 28}

Equation 6.

J i t t e r l i m i t = 0.45 \times U I

DS90UB913A-Q1 and DS90UB913Q-Q1 UI Definition and Time-Domain Jitter Limit

Equation 7.

10 - b i t M o d e : U I = \frac{1}{\frac{f_{P C L K}}{2} \times 28}

Equation 8.

12 - b i t H F M o d e : U I = \frac{1}{f_{P C L K} \times \frac{2}{3} \times 28}

Equation 9.

12 - b i t L F M o d e : U I = \frac{1}{f_{P C L K} \times 28}

Equation 10.

J i t t e r l i m i t = 0.1 \times U I

DS90UB935-Q1 DS90UB953-Q1, DS90UB953A-Q1, and DS90UB635-Q1 UI Definition and Time-Domain Jitter Limit

Equation 11.

U I = \frac{1}{f_{O S C}}

Equation 12.

J i t t e r l i m i t = 0.05 \times U I

DS90UB954-Q1, DS90UB936-Q1, DS90UB958-Q1, and DS90UB638-Q1 Frequency-Domain Jitter Limit

Phase noise integration range: 200kHz - 10MHz

Jitter limit = 50ps peak-peak

DS90UB960-Q1, DS90UB962-Q1, and DS90UB662-Q1 Frequency-Domain Jitter Limit

Phase noise integration range: 200kHz - 10MHz

Jitter limit = 50ps peak-peak

DS90Ux941AS-Q1 UI Definition and Time-Domain Jitter Limit

Equation 13.

S i n g l e - l i n k M o d e : U I = \frac{1}{f_{P C L K} \times 35}

Equation 14.

D u a l - l i n k M o d e : U I = \frac{1}{\frac{f_{P C L K}}{2} \times 35}

Equation 15.