1 Introduction

FPD-Link devices require an external clock signal for certain configurations and system applications. The jitter performance of the reference clock is typically stringent since this can contribute noise to the serializer's PLL input and can impact the horizontal eye margin of the data link. To optimize link quality, make sure the reference clock meets jitter requirements based on the system needs. This document summarizes time-domain and frequency-domain jitter requirements for all FPD-Link devices that require an external clock reference and provide a selection guide of TI's automotive grade clocking designs. TI's BAW technology is used in the CDC6C-Q1 low-power LVCMOS oscillator, as well as the LMK3H0102-Q1 and LMK1C0105-Q1 clock generators.

Note that throughout this document, REFCLK can be used as a term for external oscillator. These terms are sometimes used interchangeably across different FPD-Link device data sheets.