SNAA435 April   2025 CDC6C-Q1 , LMK3C0105-Q1 , LMK3H0102-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2FPD-Link REFCLK Requirements and Jitter Definitions
    1. 2.1 FPD-Link III REFCLK Requirements
    2. 2.2 FPD-Link IV REFCLK Requirements
  6. 3FPD-Link Clocking Selection Guide
  7. 4EMI Considerations
  8. 5Summary
  9. 6References

Abstract

This document summarizes the REFCLK requirements for FPD-Link SerDes devices and the test methodology for measuring AC parameters of the clock signal. The document also describes the measurement setup for both frequency-domain and time-domain jitter measurements. Lastly, there is a selection guide for the corresponding TI clocking device for every FPD-Link device in the FPD-Link III and FPD-Link IV product families that requires an external REFCLK.