3 FPD-Link Clocking Selection Guide

Table 3-1 and Table 3-2 summarize typical configurations and REFCLK jitter requirements for all FPD-Link III and FPD-Link IV devices that require an external oscillator. CDC6C-Q1, LMK3H0102-Q1, and LMK3C0105-Q1 jitter measurements are provided for typical REFCLK frequencies and jitter test conditions. LMK3H0102-Q1 and LMK3C0105-Q1 measurements include worst-case crosstalk with common frequency combinations (ex: 25MHz, 27MHz, and 100MHz) to represent more realistic system use cases. Time-domain measurements only include typical values. RMS phase jitter measurements in Table 3-2 also include maximum specifications across PVT based on device characterization.

If only one output frequency is needed, the CDC6C-Q1 oscillator is generally recommended. This is offered in the industry smallest package size and has minimal power consumption. If multiple output frequencies are required, a clock generator such as LMK3H0102-Q1 or LMK3C0105-Q1 can often be the simplest system design.