SNAS847E November   2023  – October 2025 LMK3H0102

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 I2C Interface Specification
  7. 6 Parameter Measurement Information
    1. 6.1 Output Format Configurations
    2. 6.2 Differential Voltage Measurement Terminology
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Block-Level Description
      2. 7.3.2 Device Configuration Control
      3. 7.3.3 OTP Mode
      4. 7.3.4 I2C Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fail-Safe Inputs
      2. 7.4.2 Fractional Output Dividers
        1. 7.4.2.1 FOD Operation
        2. 7.4.2.2 Edge Combiner
        3. 7.4.2.3 Digital State Machine
        4. 7.4.2.4 Spread-Spectrum Clocking
        5. 7.4.2.5 Integer Boundary Spurs
      3. 7.4.3 Output Behavior
        1. 7.4.3.1 Output Format Selection
          1. 7.4.3.1.1 Output Format Types
            1. 7.4.3.1.1.1 LP-HCSL Termination
        2. 7.4.3.2 Output Slew Rate Control
        3. 7.4.3.3 REF_CTRL Operation
      4. 7.4.4 Output Enable
        1. 7.4.4.1 Output Enable Control
        2. 7.4.4.2 Output Enable Polarity
        3. 7.4.4.3 Individual Output Enable
        4. 7.4.4.4 Output Disable Behavior
      5. 7.4.5 Device Default Settings
    5. 7.5 Programming
      1. 7.5.1 I2C Serial Interface
      2. 7.5.2 One-Time Programming Sequence
  9. 8 Device Registers
    1. 8.1 Register Maps
      1. 8.1.1  R0 Register (Address = 0x0) [reset = 0x0861/0x0863]
      2. 8.1.2  R1 Register (Address = 0x1) [reset = 0x5599]
      3. 8.1.3  R2 Register (Address = 0x2) [reset = 0xC28F]
      4. 8.1.4  R3 Register (Address = 0x3) [reset = 0x1801]
      5. 8.1.5  R4 Register (Address = 0x4) [reset = 0x0000]
      6. 8.1.6  R5 Register (Address = 0x5) [reset = 0x0000]
      7. 8.1.7  R6 Register (Address = 0x6) [reset = 0x0AA0]
      8. 8.1.8  R7 Register (Address = 0x7) [reset = 0x6503]
      9. 8.1.9  R8 Register (Address = 0x8) [reset = 0xC28F]
      10. 8.1.10 R9 Register (Address = 0x9) [reset = 0x3166]
      11. 8.1.11 R10 Register (Address = 0xA) [reset = 0x0010]
      12. 8.1.12 R11 Register (Address = 0xB) [reset = 0x0000]
      13. 8.1.13 R12 Register (Address = 0xC) [reset = 0xE800]
      14. 8.1.14 R146 Register (Address = 0x92) [reset = 0x0000]
      15. 8.1.15 R147 Register (Address = 0x93) [reset = 0x0000]
      16. 8.1.16 R148 Register (Address = 0x94) [reset = 0x0000]
      17. 8.1.17 R238 Register (Address = 0xEE) [reset = 0x0000]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Block Diagram Examples
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Example: Changing Output Frequency
      5. 9.2.5 Crosstalk
      6. 9.2.6 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Up Sequencing
      2. 9.3.2 Decoupling Power Supply Inputs
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.1.8 R7 Register (Address = 0x7) [reset = 0x6503]

R7 is shown in Table 8-19.

Return to the Summary Table.

Table 8-10 R7 Register Field Descriptions
Bit Field Type Reset Description
15 Reserved N/A 0x0 Reserved, do not write to this field.
14:13 REF_CTRL_PIN_FUNC R/W 0x3

Sets the function of the REF_CTRL pin. This field is stored in the EFUSE.

0h: REF_CTRL pin disabled, pulled to GND.

1h: REF_CTRL pin disabled, forced to a tri-state condition.

2h: REF_CTRL pin functions as an additional LVCMOS REF_CLK output.

3h: REF_CTRL pin functions as "clock ready" signal.
12:11 REF_CLK_DIV R/W 0x0

REF_CLK output divisor value when REF_CTRL is used as REF_CLK. This field is stored in the EFUSE.

0h: REF_CLK disabled.

1h: FOD / 2.

2h: FOD / 4.

3h: FOD / 8.
10 Reserved R/W 0x1 Reserved. Do not write any value other than '1' to this field.
9 REF_CLK_FOD_SEL R/W 0x0

Select the FOD used to generate the REF_CLK output. This field is stored in the EFUSE.

0h: FOD0.

1h: FOD1.
8 OUT1_EN R/W 0x1

Output Enable bit for OUT1. This field is stored in the EFUSE.

0h: OUT1 is disabled.

1h: OUT1 is enabled.
7 OUT1_CH_SEL R/W 0x0

Selects the source for OUT1. If the Edge Combiner is enabled, then this bit is ignored. This field is stored in the EFUSE.

0h: OUT1 is sourced from Channel Divider 0 if CH0_EDGE_COMB_EN is a '0', or the Edge Combiner if CH0_EDGE_COMB_EN is a '1'.

1h: OUT1 is sourced from Channel Divider 1 if CH1_EDGE_COMB_EN is a '0', or the Edge Combiner if CH1_EDGE_COMB_EN is a '1'.
6:5 OUT1_SLEW_RATE R/W 0x0

Slew rate control for OUT1. This field is stored in the EFUSE.

Only applies to differential output formats.

0h: Between 2.3V/ns and 3.5V/ns.

1h: Between 2.0V/ns and 3.2V/ns.

2h: Between 1.7V/ns and 2.8V/ns.

3h: Between 1.4V/ns and 2.7V/ns.
4:2 OUT1_FMT R/W 0x0

Selects the output format for OUT1. This field is stored in the EFUSE.

0h: LP-HCSL 100Ω Termination.

1h: LP-HCSL 85Ω Termination.

2h: AC-coupled LVDS.

3h: DC-coupled LVDS.

4h: LVCMOS, OUTx_P enabled, OUTx_N disabled.

5h: LVCMOS, OUTx_P disabled, OUTx_N enabled.

6h: LVCMOS, OUTx_P enabled, OUTx_N enabled, 180 degrees out of phase.

7h: LVCMOS, OUTx_P enabled, OUTx_N enabled, OUTx_P and OUTx_N in phase.
1 OUT0_EN R/W 0x1

Output Enable bit for OUT0. This field is stored in the EFUSE.

0h: OUT0 is disabled.

1h: OUT0 is enabled.
0 OE_PIN_POLARITY R/W 0x1

OE pin polarity selection. This bit does not affect the polarity of the OUTx_EN bits, only the OE pin. This field is stored in the EFUSE.

0h: OE is active high (OE tied to VDD enables outputs).

1h: OE is active low (OE tied to GND enables outputs).