SNAS855H November   2023  – October 2026 LMKDB1102 , LMKDB1104 , LMKDB1108 , LMKDB1112 , LMKDB1120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information 
    5. 6.5 Electrical Characteristics
    6. 6.6 SMBus Timing Requirements
    7. 6.7 SBI Timing Requirements
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Features
        1. 8.3.1.1 Running Input Clocks When Device is Powered Off
        2. 8.3.1.2 Fail-Safe Inputs
        3. 8.3.1.3 Input Configurations
          1. 8.3.1.3.1 Internal Termination for Clock Inputs
          2. 8.3.1.3.2 AC-Coupled or DC-Coupled Clock Inputs
      2. 8.3.2 Flexible Power Sequence
        1. 8.3.2.1 PWRDN# Assertion and Deassertion
        2. 8.3.2.2 OE# Assertion and Deassertion
        3. 8.3.2.3 Clock Input and PWRGD/PWRDN# Behaviors When Device Power is Off
      3. 8.3.3 LOS and OE
        1. 8.3.3.1 Additional OE# Pins for LMKDB1120 and Backward Compatibility
        2. 8.3.3.2 Synchronous OE
        3. 8.3.3.3 OE Control
        4. 8.3.3.4 Automatic Output Disable
        5. 8.3.3.5 LOS Detection
      4. 8.3.4 Output Features
        1. 8.3.4.1 Double Termination
        2. 8.3.4.2 Programmable Output Slew Rate
          1. 8.3.4.2.1 Slew Rate Control through Pin
          2. 8.3.4.2.2 Slew Rate Control Through SMBus
        3. 8.3.4.3 Programmable Output Swing
        4. 8.3.4.4 Accurate Output Impedance
        5. 8.3.4.5 Programmable Output Impedance
        6. 8.3.4.6 Fail-Safe Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 SMBus Mode
      2. 8.4.2 SBI Mode
      3. 8.4.3 Pin Mode
  10. 9 Register Maps
    1. 9.1 LMKDB1120 and LMKDB1120FS Registers
    2. 9.2 LMKDB1112 Registers
    3. 9.3 LMKDB1113 Registers
    4. 9.4 LMKDB1108 and LMKDB1108FS Registers
    5. 9.5 LMKDB1104 and LMKDB1104FS Registers
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 Power Supply Recommendations
    4. 10.4 Layout
      1. 10.4.1 Layout Guidelines
      2. 10.4.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Mechanical Data

5 Pin Configuration and Functions

Figure 5-1 LMKDB1120 and LMKDB1120FS 6mm × 6mm NPP Package80 Pin TLGATop View
Legend
CLOCK INPUTSCLOCK OUTPUTSPOWER
GNDLOGIC CONTROLS / STATUSNO CONNECT
Table 5-1 LMKDB1120 and LMKDB1120FS Pin Functions
PINTYPE(1)DESCRIPTION
NAME(2)(3)NO.
CLOCK INPUTS
CLKIN_PG1IDifferential clock input.
CLKIN_NH1I
CLOCK OUTPUTS
CLK0_PJ1OLP-HCSL differential clock output 0. No connect if unused.
CLK0_NK1O
CLK1_PL1OLP-HCSL differential clock output 1. No connect if unused.
CLK1_NM1O
CLK2_PM2OLP-HCSL differential clock output 2. No connect if unused.
CLK2_NM3O
CLK3_PM4OLP-HCSL differential clock output 3. No connect if unused.
CLK3_NM5O
CLK4_PM7OLP-HCSL differential clock output 4. No connect if unused.
CLK4_NM8O
CLK5_PM9OLP-HCSL differential clock output 5. No connect if unused.
CLK5_NM10O
CLK6_PM11OLP-HCSL differential clock output 6. No connect if unused.
CLK6_NM12O
CLK7_PL12OLP-HCSL differential clock output 7. No connect if unused.
CLK7_NK12O
CLK8_PJ12OLP-HCSL differential clock output 8. No connect if unused.
CLK8_NH12O
CLK9_PG12OLP-HCSL differential clock output 9. No connect if unused.
CLK9_NF12O
CLK10_PD12OLP-HCSL differential clock output 10. No connect if unused.
CLK10_NC12O
CLK11_PB12OLP-HCSL differential clock output 11. No connect if unused.
CLK11_NA12O
CLK12_PA11OLP-HCSL differential clock output 12. No connect if unused.
CLK12_NA10O
CLK13_PA9OLP-HCSL differential clock output 13. No connect if unused.
CLK13_NA8O
CLK14_PA7OLP-HCSL differential clock output 14. No connect if unused.
CLK14_NA6O
CLK15_PA5OLP-HCSL differential clock output 15. No connect if unused.
CLK15_NA4O
CLK16_PA3OLP-HCSL differential clock output 16. No connect if unused.
CLK16_NA2O
CLK17_PA1OLP-HCSL differential clock output 17. No connect if unused.
CLK17_NB1O
CLK18_PC1OLP-HCSL differential clock output 18. No connect if unused.
CLK18_ND1O
CLK19_PE1OLP-HCSL differential clock output 19. No connect if unused.
CLK19_NF1O
POWER
VDDAH2PAnalog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLKB2, B6, B11, L2, L11POutput power supply
Thermal Pad (GND)PadGDevice Ground, Thermal pad.
LOGIC CONTROLS / STATUS
vOE0#/NCJ2IActive low input to control CLK0. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE1#/NCK2IActive low input to control CLK1. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE2#/NCL3IActive low input to control CLK2. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE3#/NCL6IActive low input to control CLK3. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE4#/NCL9IActive low input to control CLK4. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE5#/SBI_INL8IActive low input to control CLK5 or SBI data input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor.

OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI data input.

vOE6#/SBI_CLKL10IActive low input to control CLK6 or SBI clock input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor.

OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI clock input.

vOE7#K11IActive low input to control CLK7. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE8#H11IActive low input to control CLK8. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE9#E12IActive low input to control CLK9. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE10#/SHFT_LD#E11IActive low input to control CLK10 or SBI active low shift register load pin. SBI_EN pin controls function of this pin. Internal pulldown resistor.

OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI shift register load input.

vOE11#C11IActive low input to control CLK11. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE12#B10IActive low input to control CLK12. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE13#/NCB9IActive low input to control CLK13. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE14#/NCB7IActive low input to control CLK14. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE15#/NCB5IActive low input to control CLK15. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE16#/NCB3IActive low input to control CLK16. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE17#/NCD2IActive low input to control CLK17. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE18#/NCD11IActive low input to control CLK18. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

vOE19#/NCJ11IActive low input to control CLK19. Internal pulldown resistor. This pin can be left no connect to match with DB2000QL pinout.

0 = Output Active, 1 = Output Inactive

SBI_OUT/NCC2OSBI data output pin/No connect. This pin can be left no connect to match with DB2000QL pinout.
vPWRGD/PWRDN#M6IPower Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode

vSBI_ENE2ISBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin L8, L10 and E11 function as OE pins. High at power-up = SBI interface enabled.

Pin L8, L10 and E11 function as SBI interface pins. SMBus and other OE pins remain functional.

^vSADR1_triB8ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_triB4ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
LOS#/NCG11OLoss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor. This pin can be left no connect to match with DB2000QL pinout.

Low = Invalid input clock.

High = Valid input clock.

SMB_DATAL4I/OSMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLKL5ISMBus Clock. Requires external pullup resistor. No connect if unused.
NC F2, F11, G2, L7NCNo connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating. Pins with "^/v" have an internal pullup or pulldown based on selected function.
(3) The "#" symbol indicates active low.
Figure 5-2 LMKDB1113 7mm × 7mm VQFN Package56 PinTop View
Legend
CLOCK INPUTSCLOCK OUTPUTSPOWER
GNDLOGIC CONTROLS / STATUSNO CONNECT
Table 5-2 LMKDB1113 Pin Functions
PINTYPE(1)DESCRIPTION
NAME(2)(3)NO.
CLOCK INPUTS
CLKIN_P8IDifferential clock input.
CLKIN_N9I
CLOCK OUTPUTS
CLK0_P12OLP-HCSL differential clock output 0. No connect if unused.
CLK0_N13O
CLK1_P18OLP-HCSL differential clock output 1. No connect if unused.
CLK1_N19O
CLK2_P20OLP-HCSL differential clock output 2. No connect if unused.
CLK2_N21O
CLK3_P23OLP-HCSL differential clock output 3. No connect if unused.
CLK3_N24O
CLK4_P26OLP-HCSL differential clock output 4. No connect if unused.
CLK4_N27O
CLK5_P31OLP-HCSL differential clock output 5. No connect if unused.
CLK5_N32O
CLK6_P34OLP-HCSL differential clock output 6. No connect if unused.
CLK6_N35O
CLK7_P37OLP-HCSL differential clock output 7. No connect if unused.
CLK7_N38O
CLK8_P39OLP-HCSL differential clock output 8. No connect if unused.
CLK8_N40O
CLK9_P43OLP-HCSL differential clock output 9. No connect if unused.
CLK9_N44O
CLK10_P47OLP-HCSL differential clock output 10. No connect if unused.
CLK10_N48O
CLK11_P50OLP-HCSL differential clock output 11. No connect if unused.
CLK11_N51O
CLK12_P53OLP-HCSL differential clock output 12. No connect if unused.
CLK12_N54O
POWER
VDDA7PAnalog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK11, 16, 30, 41, 49, POutput power supply
Thermal Pad (GND)PadGDevice Ground, Thermal pad.
LOGIC CONTROLS / STATUS
^OE0#10IActive low input to control CLK0. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^/vOE1#/SHFT_LD#17IActive low input to control CLK1 or SBI active low shift register load pin. SBI_EN pin controls function of this pin. OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI latch register input.

^OE2#22IActive low input to control CLK2. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE3#25IActive low input to control CLK3. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE4#28IActive low input to control CLK4. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^/vOE5#/SBI_IN29IActive low input to control CLK5 or SBI data input pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI data input.

^OE6#33IActive low input to control CLK6. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE7#36IActive low input to control CLK7. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^/vOE8#/SBI_CLK42IActive low input to control CLK9 or SBI clock input pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI clock input.

^OE9#45IActive low input to control CLK9. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE10#/SBI_OUT46I or OActive low input to control CLK10 or SBI data output pin. Internal pullup resistor. SBI_EN pin controls function of this pin.

OE mode with an internal pullup: 0 = Active output, 1 = Inactive output.

SBI Mode: SBI shift register data output.

^OE11#52IActive low input to control CLK11. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE12#55IActive low input to control CLK12. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^PWRGD/PWRDN#15IPower Good/Power Down Active Low. Multifunctional input pin. Internal pullup resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode

vSBI_EN14ISBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin 20, 32, 48 and 55 function as OE pins.

High at power-up = SBI interface enabled. Pin 20, 32, 48 and 55 function as SBI interface pins. SMBus and other OE pins remain functional.

^vSADR1_tri3ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_tri4ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^SLEWRATE_SEL2ILP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.

LOS#1OLoss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.

SMB_DATA5I/OSMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK6ISMBus Clock. Requires external pullup resistor. No connect if unused.
NC56NCNo connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3) The "#" symbol indicates active low.
Figure 5-3 LMKDB1112 5mm × 5mm Package 64 Pin LGA Top View
Legend
CLOCK INPUTSCLOCK OUTPUTSPOWER
GNDLOGIC CONTROLS / STATUSNO CONNECT
Table 5-3 LMKDB1112 Pin Functions
PINTYPE(1)DESCRIPTION
NAME(2)(3)NO.
CLOCK INPUTS
CLKIN_PE1IDifferential clock input.
CLKIN_NF1I
CLOCK OUTPUTS
CLK0_NA2OLP-HCSL differential clock output 0. No connect if unused.
CLK0_PA3O
CLK1_NA4OLP-HCSL differential clock output 1. No connect if unused.
CLK1_PA5O
CLK2_NA6OLP-HCSL differential clock output 2. No connect if unused.
CLK2_PA7O
CLK3_NA8OLP-HCSL differential clock output 3. No connect if unused.
CLK3_PA9O
CLK4_PC10OLP-HCSL differential clock output 4. No connect if unused.
CLK4_NB10O
CLK5_PE10OLP-HCSL differential clock output 5. No connect if unused.
CLK5_ND10O
CLK6_PG10OLP-HCSL differential clock output 6. No connect if unused.
CLK6_NF10O
CLK7_PJ10OLP-HCSL differential clock output 7. No connect if unused.
CLK7_NH10O
CLK8_PK8OLP-HCSL differential clock output 8. No connect if unused.
CLK8NK9O
CLK9_PK6OLP-HCSL differential clock output 9. No connect if unused.
CLK9_NK7O
CLK10_PK4OLP-HCSL differential clock output 10. No connect if unused.
CLK10_NK5O
CLK11_PH1OLP-HCSL differential clock output 11. No connect if unused.
CLK11_NJ1O
POWER
VDDAF2PAnalog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLKB5, C9, H2, H9, J3POutput power supply
GNDD4, D5,D6, D7,E4, E5,E6, E7,F4, F5, F6, F7,G4, G5,G6, G7GDevice Ground pin.
LOGIC CONTROLS / STATUS
^OE0#B3IActive low input to control CLK0. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE1#B4IActive low input to control CLK1. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^/vOE2#/SBI_OUTB7I or OActive low input to control CLK2 or SBI data output pin. Internal pullup resistor. SBI_EN pin controls function of this pin.

OE mode with an internal pullup: 0 = Active output, 1 = Inactive output.

SBI Mode: SBI shift register data output.

^OE3#B8IActive low input to control CLK3. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^/vOE4#/SBI_CLKA10I

Active low input to control CLK4 or SBI clock input pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI clock input.

^OE5#E9IActive low input to control CLK5. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE6#G9IActive low input to control CLK6. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^/vOE7#/SBI_INK10I

Active low input to control CLK7 or SBI data input pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI data input.

^OE8#J8IActive low input to control CLK8. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE9#J6IActive low input to control CLK9. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE10#/SHFT_LD#J4I

Active low input to control CLK10 or SBI active low shift register load pin. SBI_EN pin controls function of this pin. OE mode with internal pullup: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI latch register input.

^OE11#G1IActive low input to control CLK11. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^PWRGD/PWRDN#K2IPower Good/Power Down Active Low. Multifunctional input pin. Internal pullup resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode

vSBI_ENK1ISBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin L8, L10 and E11 function as OE pins. High at power-up = SBI interface enabled.

Pin L8, L10 and E11 function as SBI interface pins. SMBus and other OE pins remain functional.

^vSADR1_triB1ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_triC1ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^SLEWRATE_SELC2ILP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.

LOS#A1OLoss of Input Clock Signal Active Low. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.

SMB_DATAD2I/OSMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLKD1ISMBus Clock. Requires external pullup resistor. No connect if unused.
NC B2, B6, B9, D9, E2, F9, G2, J2, J5, J7, J9, K3NCNo connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating. Pins with "^/v" have an internal pullup or pulldown based on selected function.
(3) The "#" symbol indicates active low.
Figure 5-4 LMKDB1108 and LMKDB1108FS 5mm x 5mm VQFN Package40 PinTop View
Legend
CLOCK INPUTSCLOCK OUTPUTSPOWER
GNDLOGIC CONTROLS / STATUSNO CONNECT
Table 5-4 LMKDB1108 and LMKDB1108FS Pin Functions
PINTYPE(1)DESCRIPTION
NAME(2)(3)NO.
CLOCK INPUTS
CLKIN_P8IDifferential clock input.
CLKIN_N9I
CLOCK OUTPUTS
CLK0_P15OLP-HCSL differential clock output 0. No connect if unused.
CLK0_N16O
CLK1_P17OLP-HCSL differential clock output 1. No connect if unused.
CLK1_N18O
CLK2_P22OLP-HCSL differential clock output 2. No connect if unused.
CLK2_N23O
CLK3_P24OLP-HCSL differential clock output 3. No connect if unused.
CLK3_N25O
CLK4_P28OLP-HCSL differential clock output 4. No connect if unused.
CLK4_N29O
CLK5_P31OLP-HCSL differential clock output 5. No connect if unused.
CLK5_N32O
CLK6_P35OLP-HCSL differential clock output 6. No connect if unused.
CLK6_N36O
CLK7_P38OLP-HCSL differential clock output 7. No connect if unused.
CLK7_N39O
POWER
VDDA7PAnalog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK10, 13, 20, 26, 37, POutput power supply
Thermal Pad (GND)PadGDevice Ground, Thermal pad.
LOGIC CONTROLS / STATUS
vOE0#/SHFT_LD#14IActive low input to control CLK0 or SBI active low shift register load pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI latch register input.

vOE1#/SBI_IN19IActive low input to control CLK1 or SBI data input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI data input.

vOE2#21IActive low input to control CLK2. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE3#27IActive low input to control CLK3. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE4#/SBI_CLK30IActive low input to control CLK4 or SBI clock input pin. SBI_EN pin controls function of this pin. Internal pulldown resistor. OE mode: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI clock input.

vOE5#33IActive low input to control CLK5. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vOE6#/SBI_OUT34I or OActive low input to control CLK6 or SBI data output pin. Internal pulldown resistor. SBI_EN pin controls function of this pin.

OE mode:0 = Active output, 1 = Inactive output.

SBI Mode: SBI shift register data output.

vOE7#40IActive low input to control CLK7. Internal pulldown resistor.

0 = Output Active, 1 = Output Inactive

vPWRGD/PWRDN#12IPower Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode

vSBI_EN11ISBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin 20, 32, 48 and 55 function as OE pins.

High at power-up = SBI interface enabled. Pin 20, 32, 48 and 55 function as SBI interface pins. SMBus and other OE pins remain functional.

^vSADR1_tri3ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_tri4ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^SLEWRATE_SEL2ILP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.

LOS#1OLoss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.

SMB_DATA5I/OSMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK6ISMBus Clock. Requires external pullup resistor. No connect if unused.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3) The "#" symbol indicates active low.
Figure 5-5 LMKDB1104 and LMKDB1104FS 4mm x 4mm VQFN Package28 PinTop View
Legend
CLOCK INPUTSCLOCK OUTPUTSPOWER
GNDLOGIC CONTROLS / STATUSNO CONNECT
Table 5-5 LMKDB1104 and LMKDB1104FS Pin Functions
PINTYPE(1)DESCRIPTION
NAME(2)(3)NO.
CLOCK INPUTS
CLKIN_P6IDifferential clock input.
CLKIN_N7I
CLOCK OUTPUTS
CLK0_P12OLP-HCSL differential clock output 0. No connect if unused.
CLK0_N13O
CLK1_P16OLP-HCSL differential clock output 1. No connect if unused.
CLK1_N17O
CLK2_P19OLP-HCSL differential clock output 2. No connect if unused.
CLK2_N20O
CLK3_P23OLP-HCSL differential clock output 3. No connect if unused.
CLK3_N24O
POWER
VDDA5PAnalog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK10, 15, 18, 25POutput power supply
Thermal Pad (GND)PadGDevice Ground, Thermal pad.
LOGIC CONTROLS / STATUS
^OE0#/vSHFT_LD#11IActive low input to control CLK0 or SBI active low shift register load pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup. LMKDB1104FS has internal pulldown: 0 = Active output, 1 = Inactive output.

Side-Band Mode: SBI latch register input.

^OE1#/vSBI_IN14IActive low input to control CLK1 or SBI data input pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup. LMKDB1104FS has internal pulldow: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI data input.

^OE2#/vSBI_CLK21IActive low input to control CLK2 or SBI clock input pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup. LMKDB1104FS has internal pulldow: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI clock input.

^OE3#/vSBI_OUT22I or OActive low input to control CLK3 or SBI data output pin. SBI_EN pin controls function of this pin.

OE mode with internal pullup. LMKDB1104FS has internal pulldown: 0 = Active output, 1 = Inactive output.

Side-Band Mode with internal pulldown: SBI shift register data output.

vPWRGD/PWRDN#9IPower Good/Power Down Active Low. Multifunctional input pin. Internal pulldown resistor.

On the first low-to-high transition, functions as Power Good pin which starts up the device

On the subsequent low/high transitions, functions as Power Down Active Low pin which controls the device to enter or exit power-down mode.

Low = power-down mode

High = normal operation mode

vSBI_EN8ISBI Enable. Internal pulldown resistor. Do not change the state of this pin after power-up.

Low at power-up = SBI interface disabled. Pin 20, 32, 48 and 55 function as OE pins.

High at power-up = SBI interface enabled. Pin 20, 32, 48 and 55 function as SBI interface pins. SMBus and other OE pins remain functional.

^vSADR1_tri1ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^vSADR0_tri2ISMBus Address 3-level input pin. Internal pullup and pulldown resistors.
^SLEWRATE_SEL27ILP-HCSL differential clock output slew rate select pin. Internal pullup resistor.

Low = Slow slew rate.

High = Fast slew rate.

LOS#28OLoss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.

SMB_DATA3I/OSMBus Data. Requires external pullup resistor. No connect if unused.
SMB_CLK4ISMBus Clock. Requires external pullup resistor. No connect if unused.
NC 26NCNo connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3) The "#" symbol indicates active low.
Figure 5-6 LMKDB1102 3mm x 3mm VQFN Package20 PinTop View
Legend
CLOCK INPUTSCLOCK OUTPUTSPOWER
GNDLOGIC CONTROLS / STATUSNO CONNECT
Table 5-6 LMKDB1102 Pin Functions
PINTYPE(1)DESCRIPTION
NAME(2)(3)NO.
CLOCK INPUTS
CLKIN_P1IDifferential clock input.
CLKIN_N2I
CLOCK OUTPUTS
CLK1_P16OLP-HCSL differential clock output 1. No connect if unused.
CLK1_N17O
CLK2_P9OLP-HCSL differential clock output 2. No connect if unused.
CLK2_N10O
POWER
VDDA6PAnalog power supply. Additional power supply filtering is recommended. See Section 10.3 for details.
VDDCLK3, 8, 14, 18, 19POutput power supply
GND7, 20GDevice Ground, Thermal pad.
Thermal Pad (GND)PadGDevice Ground, Thermal pad.
LOGIC CONTROLS / STATUS
^OE1#15IActive low input to control CLK1. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

^OE2#12IActive low input to control CLK2. Internal pullup resistor.

0 = Output Active, 1 = Output Inactive

LOS#13OLoss of Input Clock Signal Active Low/No Connect. Open drain. Requires external pullup resistor.

Low = Invalid input clock.

High = Valid input clock.

vZOUT_SEL11ILP-HCSL differential clock output impedance select. Internal pulldown resistor.

Low = 85Ω.

High = 100Ω.

NC 4, 5NCNo connect.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, NC = No Connect
(2) Pins with a "^" prefix have an internal pullup resistor. Pins with a "v" prefix have an internal pulldown resistor. Pins with a "^v" have an internal pullup resistor and an internal pulldown resistor so that mid level is selected when the pin is left floating.
(3) The "#" symbol indicates active low.