SNAU292 August   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  7. 2Hardware
    1. 2.1 Setup
      1. 2.1.1  Evaluation Setup Requirement
      2. 2.1.2  Connection Diagram
      3. 2.1.3  How to Enable Full SPI Control
      4. 2.1.4  Power Requirements
      5. 2.1.5  Pin Mode Strapping
      6. 2.1.6  Reference Clock
      7. 2.1.7  Output Connections
      8. 2.1.8  Header Information
      9. 2.1.9  Default Configuration
      10. 2.1.10 How to Generate SYSREF
      11. 2.1.11 Multiplier Mode Example
      12. 2.1.12 Divider Mode Example
      13. 2.1.13 Hybrid Mode: SPI and Pin Mode
  8. 3Software
    1. 3.1 Software Installation
    2. 3.2 Software Description
    3. 3.3 USB2ANY Interface
  9. 4Implementation Results
    1. 4.1 Buffer, Divider, and Multiplier Modes
    2. 4.2 SYSREF Generation
    3. 4.3 SYSREF Delay Generators
  10. 5Hardware Design Files
    1. 5.1 Schematic
    2. 5.2 PCB Layout
    3. 5.3 PCB Layer Stack-Up
    4. 5.4 Bill of Materials
  11. 6Additional Information
    1. 6.1 Troubleshooting Guide
      1. 6.1.1 General Guidance
      2. 6.1.2 If Output Is Not Seen on CLKOUT
      3. 6.1.3 If Device Features Are Not Active
      4. 6.1.4 If Multiplier Frequency Is Not Accurate
      5. 6.1.5 If Divider Frequency Is Not Accurate
      6. 6.1.6 If SYSREF Is Not Observed
    2. 6.2 Trademarks

4.1 Buffer, Divider, and Multiplier Modes

From the top-menu, click Default Configuration → 3200MHz Buffer Mode. This automatically loads the buffer mode profile.

If termination is not applied on all output pins, then manually disable the unused outputs using the CHx_EN fields (to completely power down unused channels) or the CLKOUTx_EN, SYSOUTx_EN, and LOGICLK_EN/LOGISYS_EN fields (to power down output buffers only). Powering down unused channels greatly reduces current consumption, and for the logic clocks in particular can reduce spurious interference.

After the profile is loaded and required any changes have been made, click USB Communications → Write All Registers to program the device.

In all of the following plots, the blue trace is the 3.2GHz reference clock from SMA100B and the black trace is the output clock from the device.

LMX1404EPEVM Buffer Mode Signal Analyzer Plot Figure 4-1 Buffer Mode Signal Analyzer Plot

To activate the multiplier or the divider, change the CLK_MUX field to specify divider or multiplier modes, and change the CLK_DIV and CLK_MULT fields to specify the frequency scaling factor.

LMX1404EPEVM Divide-by-2 Mode Signal Analyzer Plot Figure 4-2 Divide-by-2 Mode Signal Analyzer Plot
LMX1404EPEVM Multiplier x4 Mode Signal Analyzer Plot Figure 4-3 Multiplier x4 Mode Signal Analyzer Plot