SNLA308A April   2019  – October 2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Trademarks
  2. 1 Introduction
  3. 2 Superframe Requirements
    1. 2.1 Left/Right 3D Format
    2. 2.2 Alternate Line 3D Format
    3. 2.3 Alternate Pixel 3D Format
  4. 3 Video Processing Status Monitoring
    1. 3.1 VIDEO_3D_STS Register (Address = 58h) [reset = 0h]
  5. 4 Superframe Splitting
  6. 5 Frame Cropping
    1. 5.1 Cropping Control Registers
      1. 5.1.1 CROP_START_X0_CROP_START_X0_P1 Register (Address = 36h) [reset = 0h]
      2. 5.1.2 CROP_START_X1_CROP_START_X1_P1 Register (Address = 37h) [reset = 0h]
      3. 5.1.3 CROP_STOP_X0_CROP_STOP_X0_P1 Register (Address = 38h) [reset = 0h]
      4. 5.1.4 CROP_STOP_X1_CROP_STOP_X1_P1 Register (Address = 39h) [reset = 0h]
      5. 5.1.5 CROP_START_Y0_CROP_START_Y0_P1 Register (Address = 3Ah) [reset = 0h]
      6. 5.1.6 CROP_START_Y1_CROP_START_Y1_P1 Register (Address = 3Bh) [reset = 0h]
      7. 5.1.7 CROP_STOP_Y0_CROP_STOP_Y0_P1 Register (Address = 3Ch) [reset = 0h]
      8. 5.1.8 CROP_STOP_Y1_CROP_STOP_Y1_P1 Register (Address = 3Dh) [reset = 0h]
    2. 5.2 Cropping Options
  7. 6 Splitter Mode Pixel Clocks
    1. 6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]
    2. 6.2 SPLIT_CLK_CTL1_SPLIT_CLK_CTL1_P1 Register (Address = 3Fh) [reset = 2h]
  8. 7 Programming Example
  9. 8 Summary
  10. 9 References
  11. 10Handling Interrupts With the DS90Ux941AS-Q1
    1. 10.1 Interrupt Control and Status (INTB and REM_INTB Pin)
    2. 10.2 Handling Interrupts in Splitter Mode Using Remote Interrupt Pin (REM_INTB)
    3. 10.3 REM_INTB_CTRL Register (Address = 30h) [reset = 0h]
  12. 11High-Speed GPIO Operation in Splitter Mode
    1. 11.1 Introduction
    2. 11.2 High-Speed Control Configuration
      1. 11.2.1 DES_CAP1 Registers (Address = 20h)
      2. 11.2.2 DES_CAP2 Registers (Address = 21h)
    3. 11.3 Back Channel Frequency Configuration
    4. 11.4 Splitter Mode GPIO
    5. 11.5 GPIO_0_Config Register (Address = Dh) [reset = 20h]
    6. 11.6 GPIO_1_and_GPIO_2_Config Register (Address = Eh) [reset = 0h]
    7. 11.7 GPIO_3_Config Register (Address = Fh) [reset = 0h]
  13.   Revision History

6.1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register (Address = 3Eh) [reset = 81h]

SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 is described in Table 6-1.

Table 6-1 SPLIT_CLK_CTL0_SPLIT_CLK_CTL0_P1 Register Field Descriptions
BitFieldTypeResetDescription
7SPLIT_CLK_DIV_EN_SP LIT_CLK_DIV_EN_P1R/W1hSplitter Mode Clock Control Register 0.
This controls the selected FPD-Link III port.
Splitter mode clock divider enable.
This register enables the splitter mode clock divider. In splitter mode, if this register is set to 0, the pixel clock for splitter operation is disabled. The divider should be disabled prior to changing the Splitter Divider settings, SPLIT_CLK_SEL, SPLIT_CLK_DIV_M, and SPLIT_CLK_DIV_N. In addition, changes to divider settings must only be done when the DSI input is disabled to ensure proper mode transition.
These values are ignored if Splitter mode is disabled. This controls the selected FPD-Link III port.
6-5SPLIT_CLK_SELR/W0hSplitter mode clock select.
This register selects the clock source for the FPD-Link III transmit side of the splitter operation for the selected port.
00 : Input pixel clock divided by 2 (default).
01 : M/N divider from the DPHY input clock.
10 : M/N divider from the external clock on the REFCLK0 pin.
11 : M/N divider from the external clock on the REFCLK1 pin.
4-0SPLIT_CLK_DIV_M_SPLI T_CLK_DIV_M_P1R/W1hSplitter mode clock divider M value.
This register controls the M setting for the M/N divider used to generate the splitter mode pixel clock from the selected input clock.
The default settings for M/N provide a half clock frequency normally required for splitting symmetric video.
These values are ignored if Splitter mode is disabled. This controls the selected FPD-Link III port.