SNLA356 September   2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2MIPI DSI Source Requirements
    1. 2.1 Supported DSI Modes
    2. 2.2 Clocking Rates and Clock Type
    3. 2.3 Blanking or Low Power Modes (BLLP)
    4. 2.4 DSI Packet Timing
      1. 2.4.1 Non-Burst Mode With Sync Pulses
      2. 2.4.2 Non-Burst Mode With Sync Events
      3. 2.4.3 Burst Mode
  5. 3Bring-Up and Debug Flow
  6. 4Example Bringup Scenarios
    1. 4.1 Discontinuous Clock
    2. 4.2 Missing Periodic Low Power Transitions
    3. 4.3 Incorrect DSI Packet Timing
    4. 4.4 THS-SKIP Configuration
    5. 4.5 End of Transmission Packets (EoTp)
    6. 4.6 Configuration of Sync Width for Event Mode/Burst Mode
  7. 5Summary
  8. 6References

1 Introduction

The DS90UB941AS-Q1 MIPI DSI serializer enables low latency bridging of a processor video source to a remote display panel or SoC across twisted pair or coaxial cabling. Since the DS90UB941AS-Q1 serializer is compatible with multiple FPD-Link deserializer products, it also enables easy video format conversion from MIPI DSI to MIPI CSI-2, OpenLDI, RGB, or other protocols depending on the application requirement.

When working with multiple video protocols and high speed serializer/deserializer devices, it is important for the system designer to have a systematic approach to determining the root cause of application issues so that they can be quickly resolved. This guide will walk through some of the key considerations that the system designer should be aware of, specifically regarding the MIPI DSI interface between the video source, and the DS90UB941AS-Q1 FPD-Link III serializer. Some examples will be provided for common issue symptoms and the approach to resolving the problem.