SNLA356 September   2020 DS90UB941AS-Q1 , DS90UH941AS-Q1

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2MIPI DSI Source Requirements
    1. 2.1 Supported DSI Modes
    2. 2.2 Clocking Rates and Clock Type
    3. 2.3 Blanking or Low Power Modes (BLLP)
    4. 2.4 DSI Packet Timing
      1. 2.4.1 Non-Burst Mode With Sync Pulses
      2. 2.4.2 Non-Burst Mode With Sync Events
      3. 2.4.3 Burst Mode
  5. 3Bring-Up and Debug Flow
  6. 4Example Bringup Scenarios
    1. 4.1 Discontinuous Clock
    2. 4.2 Missing Periodic Low Power Transitions
    3. 4.3 Incorrect DSI Packet Timing
    4. 4.4 THS-SKIP Configuration
    5. 4.5 End of Transmission Packets (EoTp)
    6. 4.6 Configuration of Sync Width for Event Mode/Burst Mode
  7. 5Summary
  8. 6References

2.4 DSI Packet Timing

DS90UB941AS-Q1 utilizes received MIPI DSI packet timing in order to reconstruct horizontal and vertical sync timing along with the video data enable signal. This allows the serializer to convert the DSI input into a generic 24 bit + sync signal DPI (Display Parallel Interface) format which can then be converted to a number of other protocols by the partner deserializer device in the system (eg. CSI-2, OpenLDI, RGB). Four types of DSI short packets are used to define the horizontal and vertical sync signal boundaries:

  • HSS (Horizontal Sync Start) - Establishes the rising edge of the horizontal sync signal

  • HSE (Horizontal Sync End) - Establishes the falling edge of the horizontal sync signal.

    Note: HSE is only utilized in DSI Pulse Mode, not Event Mode or Burst mode

  • VSS (Vertical Sync Start) - Establishes the rising edge of the vertical sync signal

  • VSE (Vertical Sync End) - Established the falling edge of the vertical sync signal.

    Note: VSE is only utilized in DSI Pulse Mode, not Event Mode or Burst Mode

The Data Enable (DE) signal is automatically generated from each received DSI long packet which corresponds to an active video data line. By default, the data enable signal will be logic high during the active portion of the video line and logic low during the video blanking, but this can also be inverted through register control.

In order to accurately generate video timing for the display, a MIPI DSI transmitter must ensure that DSI packet timing matches the DPI pixel transmission rates and widths of all timing events like sync pulses according to the DSI mode which is used: