To analyze the root cause of any EtherCAT clock configuration failure, the design team created a test environment and performed simulations, as shown in Figure 3-8, where two writes to the ETHERCATCLKCTL register were executed within approximately 40 cycles. As shown in Figure 3-8, the first and second writes are marked in red (VBUS32_REQ: Yellow waveform). This write operation must configure the value of the EtherCAT clock divider, which operates in a slower clock domain (INTOSC1). Therefore, a pulse transmission from 200MHz to 10MHz is required. Under the pulse transmission signal “Pulse sync”, signals i_src_clk (source clock), i_src_pulse (source pulse), i_des_clk (destination clock), o_des_pulse (destination pulse), and des_ack (acknowledge signal from destination domain) are displayed. Any other write to this register is missed as long as the ACK signal is high. In this case, a second write to the register occurs when the des_ack signal (magenta or pink signal) is high. However, the divider never receives this value; it is only configured with the old value.