SNLA494 February   2026 DP83826E , DP83826I , TMS320F28P650DH , TMS320F28P650DK

 

  1.   1
  2.   Summary
  3.   Revision History
  4. 1Overview of EtherCAT and Communication Model
  5. 2EtherCAT Slave Frame Transmission and Diagnostics
    1. 2.1 Frame Processing at EtherCAT Slaves
    2. 2.2 ESC Diagnostics
  6. 3EtherCAT Frame Error Fault Cases and Investigation Methods
    1. 3.1 Frame Error Fault Case
    2. 3.2 Frame Error Investigation Case – Fault Isolation Analysis
      1. 3.2.1 ESC PHY0 or PHY1 Fault Isolation Analysis
      2. 3.2.2 ESC F28P65 and MII Fault Isolation Analysis
    3. 3.3 Frame Error Investigation Case – ESC Fault Investigation Within F28P65
      1. 3.3.1 EtherCAT Clock Configuration Failure Analysis
      2. 3.3.2 Recommendations for EtherCAT Clock Configuration
      3. 3.3.3 Addressing Metastability Issue During Clock Domain Crossing Using DCC
  7. 4Summary
  8. 5References

3.2.1 ESC PHY0 or PHY1 Fault Isolation Analysis

As shown in Figure 3-3, to reproduce the fault, PHY Reverse Loopback can be used to verify the operational status of ESC5 PHY0 and PHY1 individually.

Connect the Master to the leftmost ESC1 and configure PHY0 of the faulty device ESC5 to operate in the Reverse Loopback mode using the following DP83826 register configuration. Data will be looped back at the MII interface of ESC5 PHY0, enabling the verification of whether ESC5 PHY0 is working properly.

The DP83826 PHY Reverse Loopback mode is configured as follows:

0000 2100 //Disables Auto-Neg, Selects 100 Mbps
0016 0010 //Select Reverse Loopback
001F 4000 //Soft Reset

In this fault case, the Reverse Loopback test for ESC5 PHY0 shows that the Master discovers ESC1 to ESC4 normally under this configuration, and the ESC4 0x0110 register displays Port1 as Open, indicating a good link between ESC4 PHY1 and ESC5 PHY0. Additionally, the data is successfully looped back by the MII interface after passing through ESC5 PHY0; therefore, ESC5 PHY0 is not faulty.

Connect the master to the rightmost ESC7, reverse the loop direction from right to left, and apply the same Reverse Loopback configuration to PHY1 of the faulty device ESC5. Using the same method and criteria, ESC5 PHY1 can also be verified as fault-free.

Fault Isolation of PHY0 or PHY1 on Faulty Device ESC5Figure 3-3 Fault Isolation of PHY0 or PHY1 on Faulty Device ESC5