SNLA494 February   2026 DP83826E , DP83826I , TMS320F28P650DH , TMS320F28P650DK

 

  1.   1
  2.   Summary
  3.   Revision History
  4. 1Overview of EtherCAT and Communication Model
  5. 2EtherCAT Slave Frame Transmission and Diagnostics
    1. 2.1 Frame Processing at EtherCAT Slaves
    2. 2.2 ESC Diagnostics
  6. 3EtherCAT Frame Error Fault Cases and Investigation Methods
    1. 3.1 Frame Error Fault Case
    2. 3.2 Frame Error Investigation Case – Fault Isolation Analysis
      1. 3.2.1 ESC PHY0 or PHY1 Fault Isolation Analysis
      2. 3.2.2 ESC F28P65 and MII Fault Isolation Analysis
    3. 3.3 Frame Error Investigation Case – ESC Fault Investigation Within F28P65
      1. 3.3.1 EtherCAT Clock Configuration Failure Analysis
      2. 3.3.2 Recommendations for EtherCAT Clock Configuration
      3. 3.3.3 Addressing Metastability Issue During Clock Domain Crossing Using DCC
  7. 4Summary
  8. 5References

4 Summary

This article begins by introducing the basic concepts of EtherCAT communication, followed by its characteristics, principles, communication model, and the diagnostic capabilities of ESCs. Starting with a real-world frame error fault case, it presents a methodology for analyzing EtherCAT frame errors, which includes diagnostic information investigation, error accumulation and propagation analysis, and fault location isolation analysis. Furthermore, it provides recommendations for using F28P65 in EtherCAT applications, sharing analysis and debugging experience for scenarios implementing EtherCAT applications with F28P65 + DP83826.