SNLS315I April   2010  – June 2026 LMH0387

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Control Pin Electrical Characteristics
    6. 5.6  Input Mode (Equalizer) DC Electrical Characteristics
    7. 5.7  Output Mode (Cable Driver) DC Electrical Characteristics
    8. 5.8  Input Mode (Equalizer) AC Electrical Characteristics
    9. 5.9  Output Mode (Cable Driver) AC Electrical Characteristics
    10. 5.10 Input Mode (Equalizer) SPI Interface AC Electrical Characteristics
    11. 5.11 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Mode (Equalizer) Description
        1. 6.3.1.1 Input Interfacing
        2. 6.3.1.2 Output Interfacing
        3. 6.3.1.3 Carrier Detect (CD)
        4. 6.3.1.4 Carrier Detect Threshold (CDTHRESH)
        5. 6.3.1.5 Auto Sleep
      2. 6.3.2 Output Mode (Cable Driver) Description
        1. 6.3.2.1 Input Interfacing
        2. 6.3.2.2 Output Interfacing
        3. 6.3.2.3 Output Slew Rate Control
        4. 6.3.2.4 Output Enable
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 Output Mode (Cable Driver)
      2. 6.5.2 Input Mode (Equalizer)
      3. 6.5.3 Input Mode (Equalizer) SPI Register Access
        1. 6.5.3.1 SPI Write
        2. 6.5.3.2 SPI Read
        3. 6.5.3.3 Output Driver Adjustments (Register 01h)
          1. 6.5.3.3.1 Output Swing
          2. 6.5.3.3.2 Offset Voltage
        4. 6.5.3.4 Launch Amplitude Optimization (Register 02h)
          1. 6.5.3.4.1 Coarse Control
          2. 6.5.3.4.2 Fine Control
        5. 6.5.3.5 Cable Length Indicator (CLI) (Register 03h)
      4. 6.5.4 Input Mode (Equalizer) SPI Register Access
        1. 6.5.4.1 General Control (Register 00h)
          1. 6.5.4.1.1 Carrier Detect
          2. 6.5.4.1.2 Mute
          3. 6.5.4.1.3 Sleep Mode
          4. 6.5.4.1.4 Extended 3G Reach Mode
  8. 7 Register Maps
    1. 7.1 SPI Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 General Guidance for Applications
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.5.3.1 SPI Write

The SPI write is shown in Figure 5-2. The MOSI payload consists of a “0” (write command), seven address bits, and eight data bits. The SS signal is driven low, and the 16 bits are sent to the MOSI input of the LMH0387. Data is latched on the rising edge of SCK. The MISO output is normally tri-stated during this operation. After the SPI write, SS must return high.