SNLS484J February   2015  – June 2026 DP83867CR , DP83867IR

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1.     7
    2. 5.1 Unused Pins
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Power-Up Timing
    7. 6.7  Reset Timing
    8. 6.8  MII Serial Management Timing
    9. 6.9  RGMII Timing
    10. 6.10 GMII Transmit Timing
    11. 6.11 GMII Receive Timing
    12. 6.12 100Mbps MII Transmit Timing
    13. 6.13 100Mbps MII Receive Timing
    14. 6.14 10Mbps MII Transmit Timing
    15. 6.15 10Mbps MII Receive Timing
    16. 6.16 DP83867IR/CR Start of Frame Detection Timing
    17. 6.17 Timing Diagrams
    18. 6.18 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 WoL (Wake-on-LAN) Packet Detection
        1. 7.3.1.1 Magic Packet Structure
        2. 7.3.1.2 Magic Packet Example
        3. 7.3.1.3 Wake-on-LAN Configuration and Status
      2. 7.3.2 Start of Frame Detect for IEEE 1588 Time Stamp
        1. 7.3.2.1 SFD Latency Variation and Determinism
          1. 7.3.2.1.1 1000Mb SFD Variation in Leader Mode
          2. 7.3.2.1.2 1000Mb SFD Variation in Follower Mode
          3. 7.3.2.1.3 100Mb SFD Variation
      3. 7.3.3 Clock Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 MAC Interfaces
        1. 7.4.1.1 Reduced GMII (RGMII)
          1. 7.4.1.1.1 1000Mbps Mode Operation
          2. 7.4.1.1.2 1000Mbps Mode Timing
          3. 7.4.1.1.3 10Mbps and 100Mbps Mode
        2. 7.4.1.2 Gigabit MII (GMII)
        3. 7.4.1.3 Media Independent Interface (MII)
          1. 7.4.1.3.1 Nibble-wide MII Data Interface
          2. 7.4.1.3.2 Collision Detect
          3. 7.4.1.3.3 Carrier Sense
      2. 7.4.2 Serial Management Interface
        1. 7.4.2.1 Extended Address Space Access
          1. 7.4.2.1.1 Write Address Operation
          2. 7.4.2.1.2 Read Address Operation
          3. 7.4.2.1.3 Write (No Post Increment) Operation
          4. 7.4.2.1.4 Read (No Post Increment) Operation
          5. 7.4.2.1.5 Write (Post Increment) Operation
          6. 7.4.2.1.6 Read (Post Increment) Operation
          7. 7.4.2.1.7 Example of Read Operation Using Indirect Register Access
          8. 7.4.2.1.8 Example of Write Operation Using Indirect Register Access
      3. 7.4.3 Auto-Negotiation
        1. 7.4.3.1 Speed and Duplex Selection - Priority Resolution
        2. 7.4.3.2 Leader and Follower Resolution
        3. 7.4.3.3 Pause and Asymmetrical Pause Resolution
        4. 7.4.3.4 Next Page Support
        5. 7.4.3.5 Parallel Detection
        6. 7.4.3.6 Restart Auto-Negotiation
        7. 7.4.3.7 Enabling Auto-Negotiation Through Software
        8. 7.4.3.8 Auto-Negotiation Complete Time
        9. 7.4.3.9 Auto-MDIX Resolution
      4. 7.4.4 Loopback Mode
        1. 7.4.4.1 Near-End Loopback
          1. 7.4.4.1.1 MII Loopback
          2. 7.4.4.1.2 PCS Loopback
          3. 7.4.4.1.3 Digital Loopback
          4. 7.4.4.1.4 Analog Loopback
        2. 7.4.4.2 External Loopback
        3. 7.4.4.3 Far-End (Reverse) Loopback
      5. 7.4.5 BIST Configuration
      6. 7.4.6 Cable Diagnostics
        1. 7.4.6.1 TDR
        2. 7.4.6.2 Energy Detect
        3. 7.4.6.3 Fast Link Drop (FLD)
        4. 7.4.6.4 Fast Link Detect
        5. 7.4.6.5 Speed Optimization
        6. 7.4.6.6 Mirror Mode
        7. 7.4.6.7 Interrupt
        8. 7.4.6.8 IEEE 802.3 Test Modes
    5. 7.5 Programming
      1. 7.5.1 Strap Configuration
      2. 7.5.2 LED Configuration
      3. 7.5.3 LED Operation From 1.8V I/O VDD Supply
      4. 7.5.4 PHY Address Configuration
      5. 7.5.5 Reset Operation
        1. 7.5.5.1 Hardware Reset
        2. 7.5.5.2 IEEE Software Reset
        3. 7.5.5.3 Global Software Reset
        4. 7.5.5.4 Global Software Restart
      6. 7.5.6 Power-Saving Modes
        1. 7.5.6.1 IEEE Power Down
        2. 7.5.6.2 Deep Power-Down Mode
        3. 7.5.6.3 Active Sleep
        4. 7.5.6.4 Passive Sleep
  9. 8 Registers
    1.     107
      1. 8.1.1   Basic Mode Control Register (BMCR)
      2. 8.1.2   Basic Mode Status Register (BMSR)
      3. 8.1.3   PHY Identifier Register #1 (PHYIDR1)
      4. 8.1.4   PHY Identifier Register #2 (PHYIDR2)
      5. 8.1.5   Auto-Negotiation Advertisement Register (ANAR)
      6. 8.1.6   Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.1.7   Auto-Negotiate Expansion Register (ANER)
      8. 8.1.8   Auto-Negotiation Next Page Transmit Register (ANNPTR)
      9. 8.1.9   Auto-Negotiation Next Page Receive Register (ANNPRR)
      10. 8.1.10  1000BASE-T Configuration Register (CFG1)
      11. 8.1.11  Status Register 1 (STS1)
      12. 8.1.12  Extended Register Addressing
        1. 8.1.12.1 Register Control Register (REGCR)
        2. 8.1.12.2 Address or Data Register (ADDAR)
      13. 8.1.13  1000BASE-T Status Register (1KSCR)
      14. 8.1.14  PHY Control Register (PHYCR)
      15. 8.1.15  PHY Status Register (PHYSTS)
      16. 8.1.16  MII Interrupt Control Register (MICR)
      17. 8.1.17  Interrupt Status Register (ISR)
      18. 8.1.18  Configuration Register 2 (CFG2)
      19. 8.1.19  Receiver Error Counter Register (RECR)
      20. 8.1.20  BIST Control Register (BISCR)
      21. 8.1.21  Status Register 2 (STS2)
      22. 8.1.22  LED Configuration Register 1 (LEDCR1)
      23. 8.1.23  LED Configuration Register 2 (LEDCR2)
      24. 8.1.24  LED Configuration Register (LEDCR3)
      25. 8.1.25  Configuration Register 3 (CFG3)
      26. 8.1.26  Control Register (CTRL)
      27. 8.1.27  Testmode Channel Control (TMCH_CTRL)
      28. 8.1.28  Robust Auto MDIX Timer Configuration Register (AMDIX_TMR_CFG)
      29. 8.1.29  Fast Link Drop Configuration Register (FLD_CFG)
      30. 8.1.30  Fast Link Drop Threshold Configuration Register (FLD_THR_CFG)
      31. 8.1.31  Configuration Register 4 (CFG4)
      32. 8.1.32  RGMII Control Register (RGMIICTL)
      33. 8.1.33  RGMII Control Register 2 (RGMIICTL2)
      34. 8.1.34  100BASE-TX Configuration (100CR)
      35. 8.1.35  Viterbi Module Configuration (VTM_CFG)
      36. 8.1.36  Skew FIFO Status (SKEW_FIFO)
      37. 8.1.37  Strap Configuration Status Register 1 (STRAP_STS1)
      38. 8.1.38  Strap Configuration Status Register 2 (STRAP_STS2)
      39. 8.1.39  BIST Control and Status Register 1 (BICSR1)
      40. 8.1.40  BIST Control and Status Register 2 (BICSR2)
      41. 8.1.41  BIST Control and Status Register 3 (BICSR3)
      42. 8.1.42  BIST Control and Status Register 4 (BICSR4)
      43. 8.1.43  Configuration for Receiver's Equalizer (CRE)
      44. 8.1.44  RGMII Delay Control Register (RGMIIDCTL)
      45. 8.1.45  ANA_LD_TXG_FINE_GAINSEL_AB (ALTFGAB)
      46. 8.1.46  ANA_LD_TXG_FINE_GAINSEL_CD (ALTFGCD)
      47. 8.1.47  ANA_LD_FILTER_TUNE_AB (ALFTAB)
      48. 8.1.48  ANA_LD_FILTER_TUNE_CD (ALFTCD)
      49. 8.1.49  Configuration of Receiver's LPF (CRLPF)
      50. 8.1.50  Enable Control of Receiver's Equalizer (ECRE)
      51. 8.1.51  PLL Clock-out Control Register (PLLCTL)
      52. 8.1.52  Transmitter Control Register (ANA_LD_DATA_CTRL)
      53. 8.1.53  DSP Configuration Register 3 (DSP_CFG3)
      54. 8.1.54  Sync FIFO Control (SYNC_FIFO_CTRL)
      55. 8.1.55  DSP Hybrid Configuration Register 2 (DSP_HYBRID_CFG2)
      56. 8.1.56  Loopback Configuration Register (LOOPCR)
      57. 8.1.57  DSP Configuration (DSP_CONFIG)
      58. 8.1.58  DSP Select Register 0 (DSP_SEL0)
      59. 8.1.59  DSP Select Register 1 (DSP_SEL1)
      60. 8.1.60  DSP Select Register 2 (DSP_SEL2)
      61. 8.1.61  DSP Follower Select Register 0 (DSP_FLR_SEL0)
      62. 8.1.62  DSP Follower Select Register 3 (DSP_FLR_SEL3)
      63. 8.1.63  DSP Follower Timing Loop Register 1 (DSP_FLR_TLOOP1)
      64. 8.1.64  DSP Follower Timing Loop Register 2 (DSP_FLR_TLOOP2)
      65. 8.1.65  DSP Feedforward Equalizer Configuration (DSP_FFE_CFG)
      66. 8.1.66  Receive Configuration Register (RXFCFG)
      67. 8.1.67  Receive Status Register (RXFSTS)
      68. 8.1.68  Pattern Match Data Register 1 (RXFPMD1)
      69. 8.1.69  Pattern Match Data Register 2 (RXFPMD2)
      70. 8.1.70  Pattern Match Data Register 3 (RXFPMD3)
      71. 8.1.71  SecureOn Pass Register 2 (RXFSOP1)
      72. 8.1.72  SecureOn Pass Register 2 (RXFSOP2)
      73. 8.1.73  SecureOn Pass Register 3 (RXFSOP3)
      74. 8.1.74  Receive Pattern Register 1 (RXFPAT1)
      75. 8.1.75  Receive Pattern Register 2 (RXFPAT2)
      76. 8.1.76  Receive Pattern Register 3 (RXFPAT3)
      77. 8.1.77  Receive Pattern Register 4 (RXFPAT4)
      78. 8.1.78  Receive Pattern Register 5 (RXFPAT5)
      79. 8.1.79  Receive Pattern Register 6 (RXFPAT6)
      80. 8.1.80  Receive Pattern Register 7 (RXFPAT7)
      81. 8.1.81  Receive Pattern Register 8 (RXFPAT8)
      82. 8.1.82  Receive Pattern Register 9 (RXFPAT9)
      83. 8.1.83  Receive Pattern Register 10 (RXFPAT10)
      84. 8.1.84  Receive Pattern Register 11 (RXFPAT11)
      85. 8.1.85  Receive Pattern Register 12 (RXFPAT12)
      86. 8.1.86  Receive Pattern Register 13 (RXFPAT13)
      87. 8.1.87  Receive Pattern Register 14 (RXFPAT14)
      88. 8.1.88  Receive Pattern Register 15 (RXFPAT15)
      89. 8.1.89  Receive Pattern Register 16 (RXFPAT16)
      90. 8.1.90  Receive Pattern Register 17 (RXFPAT17)
      91. 8.1.91  Receive Pattern Register 18 (RXFPAT18)
      92. 8.1.92  Receive Pattern Register 19 (RXFPAT19)
      93. 8.1.93  Receive Pattern Register 20 (RXFPAT20)
      94. 8.1.94  Receive Pattern Register 21 (RXFPAT21)
      95. 8.1.95  Receive Pattern Register 22 (RXFPAT22)
      96. 8.1.96  Receive Pattern Register 23 (RXFPAT23)
      97. 8.1.97  Receive Pattern Register 24 (RXFPAT24)
      98. 8.1.98  Receive Pattern Register 25 (RXFPAT25)
      99. 8.1.99  Receive Pattern Register 26 (RXFPAT26)
      100. 8.1.100 Receive Pattern Register 27 (RXFPAT27)
      101. 8.1.101 Receive Pattern Register 28 (RXFPAT28)
      102. 8.1.102 Receive Pattern Register 29 (RXFPAT29)
      103. 8.1.103 Receive Pattern Register 30 (RXFPAT30)
      104. 8.1.104 Receive Pattern Register 31 (RXFPAT31)
      105. 8.1.105 Receive Pattern Register 32 (RXFPAT32)
      106. 8.1.106 Receive Pattern Byte Mask Register 1 (RXFPBM1)
      107. 8.1.107 Receive Pattern Byte Mask Register 2 (RXFPBM2)
      108. 8.1.108 Receive Pattern Byte Mask Register 3 (RXFPBM3)
      109. 8.1.109 Receive Pattern Byte Mask Register 4 (RXFPBM4)
      110. 8.1.110 Receive Pattern Control (RXFPATC)
      111. 8.1.111 I/O Configuration (IO_MUX_CFG)
      112. 8.1.112 GPIO Mux Control Register 1 (GPIO_MUX_CTRL1)
      113. 8.1.113 GPIO Mux Control Register 2 (GPIO_MUX_CTRL2)
      114. 8.1.114 GPIO Mux Control Register (GPIO_MUX_CTRL)
      115. 8.1.115 TDR General Configuration Register 1 (TDR_GEN_CFG1)
      116. 8.1.116 TDR Threshold Configuration Register 1 (TDR_THR_CFG1)
      117. 8.1.117 TDR Threshold Configuration Register 2 (TDR_THR_CFG2)
      118. 8.1.118 TDR General Configuration Register 5 (TDR_GEN_CFG5)
      119. 8.1.119 TDR Peak Locations Register 1 (TDR_PEAKS_LOC_1)
      120. 8.1.120 TDR Peak Locations Register 2 (TDR_PEAKS_LOC_2)
      121. 8.1.121 TDR Peak Locations Register 3 (TDR_PEAKS_LOC_3)
      122. 8.1.122 TDR Peak Locations Register 4 (TDR_PEAKS_LOC_4)
      123. 8.1.123 TDR Peak Locations Register 5 (TDR_PEAKS_LOC_5)
      124. 8.1.124 TDR Peak Locations Register 6 (TDR_PEAKS_LOC_6)
      125. 8.1.125 TDR Peak Locations Register 7 (TDR_PEAKS_LOC_7)
      126. 8.1.126 TDR Peak Locations Register 8 (TDR_PEAKS_LOC_8)
      127. 8.1.127 TDR Peak Locations Register 9 (TDR_PEAKS_LOC_9)
      128. 8.1.128 TDR Peak Locations Register 10 (TDR_PEAKS_LOC_10)
      129. 8.1.129 TDR Peak Amplitudes Register 1 (TDR_PEAKS_AMP_1)
      130. 8.1.130 TDR Peak Amplitudes Register 2 (TDR_PEAKS_AMP_2)
      131. 8.1.131 TDR Peak Amplitudes Register 3 (TDR_PEAKS_AMP_3)
      132. 8.1.132 TDR Peak Amplitudes Register 4 (TDR_PEAKS_AMP_4)
      133. 8.1.133 TDR Peak Amplitudes Register 5 (TDR_PEAKS_AMP_5)
      134. 8.1.134 TDR Peak Amplitudes Register 6 (TDR_PEAKS_AMP_6)
      135. 8.1.135 TDR Peak Amplitudes Register 7 (TDR_PEAKS_AMP_7)
      136. 8.1.136 TDR Peak Amplitudes Register 8 (TDR_PEAKS_AMP_8)
      137. 8.1.137 TDR Peak Amplitudes Register 9 (TDR_PEAKS_AMP_9)
      138. 8.1.138 TDR Peak Amplitudes Register 10 (TDR_PEAKS_AMP_10)
      139. 8.1.139 TDR General Status (TDR_GEN_STATUS)
      140. 8.1.140 TDR Peak Sign AB (TDR_PEAK_SIGN_A_B)
      141. 8.1.141 TDR Peak Sign CD (TDR_PEAK_SIGN_C_D)
      142. 8.1.142 DSP Leader Step 4 Register (DSP_LDR_STEP4)
      143. 8.1.143 DSP Follower Step 4 Register (DSP_FLR_STEP4)
      144. 8.1.144 DSP Follower Step 5 Register (DSP_FLR_STEP5)
      145. 8.1.145 DSP Follower Step 6&7 Register (DSP_FLR_STEP67)
      146. 8.1.146 Programmable Gain Register (PROG_GAIN)
      147. 8.1.147 Mean Square Error Channel A Register (MSE_A)
      148. 8.1.148 Mean Square Error Channel B Register (MSE_B)
      149. 8.1.149 Mean Square Error Channel C Register (MSE_C)
      150. 8.1.150 Mean Square Error Channel D Register (MSE_D)
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Cable Line Driver
        2. 9.2.1.2 Clock In (XI) Recommendation
        3. 9.2.1.3 Crystal Recommendations
        4. 9.2.1.4 Clock Out (CLK_OUT) Phase Noise
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 MAC Interface
          1. 9.2.2.1.1 RGMII Layout Guidelines
          2. 9.2.2.1.2 GMII Layout Guidelines
        2. 9.2.2.2 Media Dependent Interface (MDI)
          1. 9.2.2.2.1 MDI Layout Guidelines
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Signal Traces
        2. 9.4.1.2 Return Path
        3. 9.4.1.3 Transformer Layout
        4. 9.4.1.4 Metal Pour
        5. 9.4.1.5 PCB Layer Stacking
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.4.6.3 Fast Link Drop (FLD)

The DP83867 includes advanced link-drop capabilities that support various real-time applications. The link drop mechanism is configurable and includes enhanced modes that allow extremely fast reaction times to link drops.

DP83867IR DP83867CR Fast Link Drop MechanismFigure 7-12 Fast Link Drop Mechanism

As described in Figure 7-12, the link loss mechanism is based on a time window search period in which the signal behavior is monitored. The T1 window is set by default to reduce typical link drops to less than 1ms in 100 = M and 0.5ms in 1000M mode.

The DP83867 supports enhanced modes that shorten the window called Fast Link Drop mode. In this mode, the T1 window is shortened significantly, in most cases less than 10μs. In this period of time, there are several criteria allowed to generate link loss event and drop the link:

  1. Loss of descrambler sync
  2. Receive errors
  3. MLT3 errors
  4. Mean Squared Error (MSE)
  5. Energy loss

The Fast Link Drop functionality allows the use of each of these options separately or in any combination. Note that because this mode enables extremely quick reaction time, the PHY is more exposed to temporary bad link quality scenarios.

Note:

When Fast Link Drop functionality is enabled on both the DUT and LP (link partner) and Link Drop is detected, the opportunity is essential to disable FLD using bit 14 of the FLD_CFG register (address 0x002D) for the link to re-establish. Once the link is up, enable FLD again using the same bit (FLD_CFG bit[14]).

As mentioned above there are five modes the PHY's FLD source can be configured to evaluate. These modes can be configured via FLD_CFG register (address 0x002D) bits[4:0]. In addition to register configuration, the 64-pin PAP package variant can also enable Fast Link Drop in Energy Loss mode via pin strapping. The pin strap sets register FLD_CFG (address 0x002D) bit[0] to high. When pin strapping is used register FLD_THR_CFG (address 0x002E) is set to 0x0222, this register must be re-configured to 0x0221.